Multiplexing Latch Circuit for Faster On-Chip Memory Testing
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Solution Overview
Problem
In integrated circuits, especially at small process nodes like 22 nm, wafer probes are fragile, making wafer-level testing unfavorable, and on-chip testing preferred, but existing solutions lack efficient methods for testing individual devices like memory and processors due to the need for multiplexers and latches that are not optimized for speed and space.
Innovation Solution
An interface circuit with a clock generator and multiplexing latch circuit that generates latching clock signals to select and latch data, reducing the number of transistors and switching delays, thereby increasing speed and reducing space occupancy, while allowing for efficient on-chip testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate multiplexer and latch are used for on-chip testing, then the testing functionality is achieved, but the transistor count and space occupancy increase
Solution Approach 1:
The patent combines the multiplexer and latch into a single integrated circuit element where the multiplexer selects between normal data and test data, and the latch stores the selected data, all within one unified structure. This merging eliminates the need for separate multiplexer and latch components, thereby reducing space occupancy and transistor count while maintaining complete testing functionality.
Solution Approach 2:
The integrated circuit element performs multiple functions: it acts as a multiplexer for data selection, a latch for data storage, and enables both normal operation mode and test mode. This multi-functionality allows a single component to replace what would traditionally require separate dedicated components for each function, reducing overall space requirements.
2Reliability
If a separate multiplexer and latch are used for on-chip testing, then the testing functionality is achieved, but the number of transistors increases
Solution Approach 1:
The patent integrates the multiplexer and latch functions into a single circuit block that shares common transistors and circuit elements. The multiplexer uses select signals to route data, and the latch uses the same structural elements to store data, eliminating redundant transistor instances that would exist in separate implementations.
Solution Approach 2:
The circuit design recovers and reuses transistor elements for multiple purposes. The same transistors that form the multiplexer switching network also serve as the latch storage elements, maximizing the utilization of each transistor and minimizing the total count required to achieve both selection and storage functions.
3Ease of operation
If traditional multiplexer and latch circuits are used, then data selection and storage are achieved, but switching delays increase
Solution Approach 1:
By merging the multiplexer and latch into a single integrated structure, the patent eliminates the cascaded switching stages that would exist between separate components. The data selection and storage occur in a unified circuit path, reducing the cumulative switching delay that accumulates when data passes through multiple separate components in sequence.
Data Source
AI summary
A memory includes a clock generator and a multiplexing latch circuit. The clock generator is configured to generate a first latching clock signal and a second latching clock signal based on a multiplexing select signal and a clock signal, and to transmit the first latching clock signal and the second latching clock signal. The multiplexing latch circuit is configured to select the first data or the second data based on the first latching clock signal and the second latching clock signal, and to store and output the selected data.