Multiplexing Latch Circuit for Faster On-Chip Test Data Selection
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Solution Overview
Problem
In integrated circuits, especially at small process nodes, wafer probes are fragile and less favorable, leading to a need for on-chip testing, which is challenging due to the inability to test individual devices like memory and processors effectively during or after manufacture.
Innovation Solution
An interface circuit with a clock generator and multiplexing latch circuit that generates latching clock signals to select and latch data, reducing the number of transistors and switching delays, thereby increasing speed and reducing space occupied in the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer probes are used for testing, then testing capability is provided, but probe fragility and reliability deteriorate at small process nodes
Solution Approach 1:
The patent extracts the testing function from external wafer probes and relocates it onto the chip itself through on-chip test circuits and multiplexing latches. This eliminates the need for fragile external probes while maintaining testing capability, directly resolving the contradiction between providing testing capability and avoiding probe fragility.
2Ease of operation
If separate multiplexer and latch circuits are used, then data selection and latching functions are provided, but transistor count and circuit complexity increase
Solution Approach 1:
The patent combines the multiplexer and latch circuits into a single integrated multiplexing latch circuit. The multiplexing latch uses shared transistors and circuit elements to perform both data selection and latching functions simultaneously, reducing the total transistor count from what would be required for separate circuits while maintaining full functionality.
Solution Approach 2:
The multiplexing latch circuit is designed to perform multiple functions using the same hardware resources. The same transistor network that performs multiplexing also performs latching, and the circuit can operate in different modes (testing mode, normal operation mode) depending on control signals, achieving multi-functionality with reduced complexity.
3Adaptability or versatility
If more transistors are used in the interface circuit, then circuit functionality is enhanced, but switching delays increase and speed decreases
Solution Approach 1:
By merging the multiplexer and latch circuits into a single integrated structure, the patent reduces the number of switching stages and interconnections between components. This consolidation eliminates redundant switching delays that would occur in separate circuits, thereby improving switching speed while maintaining enhanced functionality.
Data Source
AI summary
A multiplexing latch circuit includes first, second, and third tristate inverters and an inverter. The first tristate inverter includes an output terminal and an input terminal coupled to a first data line, the second tristate inverter includes an output terminal and an input terminal coupled to a second data line, and the third tristate inverter includes an input terminal and an output terminal. The first inverter includes an input terminal coupled to the output terminals of each of the first, second, and third tristate inverters, an output terminal coupled to the input terminal of the third tristate inverter, and is configured to generate an output signal based on data received on one of the first data line or the second data line.