Multiplexing Latch Circuit for Faster On-Chip Test Data Selection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuits, especially at small process nodes, on-chip testing is preferred due to the fragility of wafer probes, but existing methods lack efficient mechanisms for selecting and latching data sources, leading to inefficiencies in testing individual devices like memory and processors.
Innovation Solution
An interface circuit with a clock generator and multiplexing latch circuit that generates latching clock signals to select and latch data, reducing the number of transistors and switching delays, thereby increasing speed and reducing space occupancy in the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a separate multiplexer and latch are used for on-chip testing, then data selection and latching functions are achieved, but the number of transistors increases and circuit speed decreases due to multiple switching delays
Solution Approach 1:
The patent combines the multiplexer and latch into a single integrated circuit element. The multiplexer selects between multiple data inputs based on select signals, while the latch simultaneously stores the selected data, eliminating the need for separate components and reducing transistor count while maintaining testing efficiency
2Productivity
If a separate multiplexer and latch are used, then data selection and latching functions are achieved, but the circuit occupies more space in the integrated circuit
Solution Approach 1:
The patent integrates the multiplexer and latch functions into a single compact circuit structure. By sharing common transistors and circuit elements between the multiplexer and latch functions, the overall area occupied in the integrated circuit is reduced compared to using separate discrete components
3Productivity
If a separate multiplexer and latch are used, then data selection and latching functions are achieved, but the number of switching delays increases and circuit speed decreases
Solution Approach 1:
The patent creates a unified multiplexing latch circuit where the multiplexer and latch operate as an integrated system. This eliminates the need for data to pass through separate multiplexer and latch stages, reducing the number of switching delays and improving overall circuit speed for testing operations
Data Source
AI summary
A integrated circuit includes a clock generator and a multiplexing latch circuit. The clock generator generates first and second latching clock signals in response to a select signal and a clock signal having a clock signal waveform, each of the first latching clock signal and the second latching clock signal having the clock signal waveform. The multiplexing latch circuit selects either first data on a first data line or second data on a second data line based on the first latching clock signal and the second latching clock signal, and stores and outputs the selected data.