Multiplexing Output Stage Impedance Tuning for ISI Jitter Reduction
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Solution Overview
Problem
The increasing data rate requirements, particularly for 100 Gbps and 112 Gbps, are hindered by large jitter noise induced by intersymbol interference (ISI) effects, which distort signals and reduce communication reliability.
Innovation Solution
A multiplexing circuit is proposed, incorporating a first type transistor and multiple second type transistors, along with an impedance circuit that provides impedance between the gate terminal of the first type transistor and the output terminal, effectively minimizing ISI by optimizing equivalent impedance across frequency bands, thus facilitating higher bandwidth capabilities without using physical passive inductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If physical passive inductors are used to optimize impedance, then bandwidth capability is improved, but chip area consumption increases
Solution Approach 1:
The patent replaces physical passive inductors (mechanical/electrical components) with an active impedance optimization circuit comprising transistors and capacitors. This substitution eliminates the need for large-area inductor components while achieving the same impedance optimization effect through active circuitry, thereby maintaining bandwidth capability without increasing chip area.
Solution Approach 2:
The patent changes the approach from fixed passive inductor values to dynamically adjustable circuit parameters. By using transistors with controllable gate voltages and adjustable capacitor values, the impedance characteristics can be optimized without being constrained by the physical size requirements of traditional inductors, enabling flexible bandwidth adjustment on compact chip areas.
2Productivity
If data rate is increased to meet higher bandwidth requirements, then productivity is improved, but jitter noise from ISI effects increases
Solution Approach 1:
The patent implements an active impedance optimization circuit that provides feedback control to compensate for ISI effects. The circuit monitors signal characteristics and dynamically adjusts impedance parameters to minimize intersymbol interference, thereby reducing jitter noise and enabling higher data rates to be achieved reliably.
Solution Approach 2:
The patent applies preliminary compensation for ISI effects by pre-adjusting the impedance characteristics before signal transmission. The active circuit anticipates and counteracts potential ISI distortion by optimizing the frequency response in advance, preventing jitter noise from degrading signal quality at higher data rates.
Data Source
AI summary
A multiplexing circuit including a first type transistor, a second type transistor and an impedance circuit; a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the first type transistor, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the second type transistor, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.