Multiplexing Prism CMOS Imagers to Single Data Bus
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Solution Overview
Problem
Solid state imagers with fixed arrays face challenges in reconfiguration into larger or higher resolution arrays, particularly when using fixed data bus architecture.
Innovation Solution
A method utilizing a bi-directional bus to connect an array of imagers in n rows and m columns, with multiplexers generating selecting signals to enable selective access and data transfer, allowing reconfiguration of the imager array while maintaining a single data bus architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed data bus architecture is used to connect imagers, then the device complexity is reduced and manufacturing is easier, but the ability to reconfigure into larger or higher resolution arrays is limited
Solution Approach 1:
The patent implements dynamic reconfiguration capability by allowing the imager array to be dynamically assembled and disassembled. The system can transition between different array configurations (e.g., 2x2, 1x4, 4x1) by controlling the connection state of imagers to the data bus, enabling adaptability without requiring multiple fixed hardware architectures.
Solution Approach 2:
The patent segments the imager array into independent units that can be individually connected or disconnected from the data bus. Each imager or group of imagers can be independently controlled through select signals, allowing the array to be divided into functional segments that can be reconfigured based on resolution and field of view requirements.
2Device complexity
If multiple imagers are connected to a single data bus, then the device complexity is reduced, but the access time and data transfer efficiency increase
Solution Approach 1:
The patent introduces multiplexer components as intermediaries between the data bus and the imagers. These multiplexers act as mediators that control which imager is connected to the data bus at any given time, enabling efficient sequential access to multiple imagers without requiring multiple separate data buses, thus reducing complexity while managing access time.
Solution Approach 2:
The patent implements periodic scanning of imagers in a systematic sequence (e.g., row-by-row or column-by-column). The control circuit sequentially activates imagers in a predetermined pattern, allowing the data bus to access imagers in periodic cycles. This method ensures that all imagers can be accessed efficiently without requiring simultaneous connections, balancing access time with architectural simplicity.
3Ease of manufacture
If a fixed array of pixels is used, then the manufacturing process is simplified, but the resolution and field of view cannot be adjusted
Solution Approach 1:
The patent creates a dynamic imager array where the physical or logical arrangement of active pixels can be changed during operation. By controlling which imagers are connected to the data bus and how they are configured through select signals, the system can dynamically adjust the effective array size and shape, enabling resolution and field of view adjustment without changing the physical sensor structure.
Solution Approach 2:
The patent designs a universal imager array architecture where the same physical array of pixels can serve multiple functions by being configured in different ways. The same set of imagers can be arranged to provide high resolution for detailed imaging or low resolution for wide field of view, making the system multi-functional without requiring separate hardware for different imaging modes.
Data Source
AI summary
A new multiple imager array device is achieved. The device comprises, first, a bi-directional bus. An array of imagers is arranged in n rows and m columns. The n and m are positive integers. Each imager is connected to the bi-directional bus. A line of bits of any imager is accessible by a line address. Each imager has a Vmode input and an output enable input. The Vmode input and the output enable input must be enabled to allow accessing. A first multiplexer has an input and a plurality of outputs. The input is connected to a column counter. Each output is connected to the output enable input of one of the imagers. A second-multiplexer has an input and a plurality of outputs. The input is connected to a row counter. Each output is connected to the Vmode input of each imager in one of the rows.