Multiplexor Circuitry for Integrated Circuit Chip Testing
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Solution Overview
Problem
The increasing complexity of integrated circuit chips due to Moore's law has led to escalating test complexity and cost, particularly in semiconductor manufacturing, where defects are common during the R&D phase, necessitating efficient testing methods that minimize data acquisition time and wafer area usage.
Innovation Solution
The integration of multiplexor circuitry and scan chains in integrated circuit chips, allowing for flexible and programmable coupling between integrated circuits and external test systems, enabling efficient testing by bypassing portions of the test chain and optimizing data acquisition through multiplexor states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If auxiliary multiplexor circuitry is introduced to route test electrical signals between various elements and external test systems, then the volume of acquired electrical test data increases, but the device complexity increases
Solution Approach 1:
The multiplexor circuitry is designed to perform multiple functions: it routes test electrical signals between various circuit elements and external test systems, and also enables bypassing of tested elements after initial testing. This multi-functionality allows a single auxiliary structure to serve both initial routing and subsequent bypass operations, reducing the need for additional dedicated bypass circuitry and thereby limiting the increase in device complexity while still enabling increased volume of acquired electrical test data through re-use of the same multiplexor resources.
2Reliability
If separate testing of elements is performed to acquire electrical test data during early stage when defect density is high, then the reliability of individual elements is improved, but the loss of time increases due to need to test each element separately
Solution Approach 1:
The testing system dynamically reconfigures the test signal paths using multiplexor circuitry. After initial separate testing of elements is completed and their reliability is established, the multiplexors are reconfigured to create bypass paths around these tested elements. This dynamic reconfiguration allows the system to transition from a state requiring separate testing of each element to a state where tested elements can be bypassed, thereby reducing the loss of time for subsequent testing operations while maintaining the reliability benefits of the initial separate testing.
Solution Approach 2:
The system performs preliminary separate testing of individual elements to establish their reliability before implementing bypass paths. By completing the time-consuming separate testing of elements in advance (preliminary action), the system enables faster subsequent testing operations that can bypass these pre-tested elements, thereby reducing the overall loss of time while preserving the reliability assurance gained from the initial detailed testing.
3Productivity
If more scan chains are added to test more integrated circuits simultaneously, then the productivity of testing increases, but the area of wafer used for auxiliary test structures increases
Solution Approach 1:
The multiplexor circuitry enables multiple scan chains to share common routing resources and control logic. By merging the routing paths and control mechanisms for multiple scan chains into shared infrastructure rather than providing dedicated paths for each chain, the system achieves increased productivity through simultaneous testing of multiple integrated circuits while limiting the area of wafer consumed by auxiliary test structures through resource sharing and consolidation.
Data Source
AI summary
An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.