Multiplexor Select Signal Duty Cycle Equalization
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Solution Overview
Problem
Existing electronic systems face challenges in managing unequal duty cycles and overlapping select signals in multiplexors, leading to inefficiencies and potential drive fights between input signals.
Innovation Solution
An integrated circuit with select signal generating circuitry and duty cycle control loops adjusts the duty cycles of select signals to equalize them and minimize overlap, using low-pass filters and XOR gates to detect and correct phase discrepancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If select signals are generated from phase-spaced clock signals without duty cycle adjustment, then the multiplexor can operate with simple signal generation circuitry, but the select signals will have unequal duty cycles and overlapping phases causing drive fights and reduced reliability
Solution Approach 1:
The patent implements duty cycle control loops that continuously monitor the duty cycles of select signals and adjust them to maintain equal duty cycles. The control loops use feedback from duty cycle detection circuitry to dynamically correct any deviations, ensuring reliable operation while automatically adapting to process variations and temperature changes.
Solution Approach 2:
The patent dynamically adjusts the duty cycle parameter of select signals to maintain optimal values despite variations in operating conditions. By changing the duty cycle parameter through controlled adjustment rather than fixed design, the system achieves reliable signal integrity across different process corners and temperatures.
2Reliability
If duty cycle control loops are implemented to equalize select signals, then signal overlap is minimized and drive fights are prevented, but the device complexity and power consumption increase
Solution Approach 1:
The duty cycle control loops operate periodically rather than continuously, adjusting select signals at specific intervals to maintain equal duty cycles. This periodic operation reduces power consumption compared to continuous adjustment while still preventing signal overlap and drive fights during critical operation periods.
Solution Approach 2:
The control loops are designed to automatically detect and correct duty cycle imbalances without external intervention. The system self-regulates by monitoring its own select signals and making necessary adjustments, eliminating the need for additional control overhead and reducing overall power consumption.
3Adaptability or versatility
If N-input multiplexor with N>3 is used, then more input signals can be selected, but the number of select signals and complexity of duty cycle control increases
Solution Approach 1:
The patent divides the duty cycle control function into separate control loops for different phases of select signals. Each control loop independently manages a specific phase, breaking down the complex N-input multiplexor control into manageable segments. This segmentation makes the system scalable and easier to implement for large N values while maintaining equal duty cycles across all select signals.
Solution Approach 2:
The duty cycle control loops are designed with universal functionality that can be applied to any N-input multiplexor configuration. The same control mechanism works for 4-input, 8-input, or larger multiplexors, providing a scalable solution that increases adaptability without proportionally increasing complexity.
Data Source
AI summary
An N-input (e.g., 4) multiplexor may receive N number of select signals. Select signal generating circuitry may receive N number of clock signals at a phase spacing that is substantially at 360 degrees divided by N (e.g., 90 degrees for N=4). The select signal generating circuitry may produce a coarse set of N number of select signals that may have unequal duty cycles and/or overlap. Duty cycle feedback control loops may be used to adjust respective duty cycles of the coarse select signals to produce select signals that have equal duty cycles and do not overlap.