Digital Multiplexor Switching to Prevent Output Clock Glitches
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Solution Overview
Problem
Digital signal multiplexors face challenges in maintaining consistent output clock signal pulses when switching between input signals, leading to premature truncation and glitches, especially when input signals stop and start at unknown times.
Innovation Solution
A digital signal multiplexor with signal loss detection circuitry, decoding circuitry, and synchronized multiplexor circuitry that selects an input clock signal with a minimum pulse duration, resetting the output signal to a predetermined state before switching to another input signal, thereby preventing glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If simple multiplexor switching is used between input clock signals, then device complexity is reduced, but output signal glitches occur due to premature truncation
Solution Approach 1:
The patent applies preliminary action by detecting signal loss conditions before they cause output glitches. The signal loss detection circuitry monitors input clock signals and proactively triggers reset sequences and switching mode changes before truncation occurs, preventing the harmful effect rather than correcting it afterward.
Solution Approach 2:
The patent introduces intermediary elements between the simple multiplexor and the output signal. These include signal loss detection circuitry, reset circuitry, and switching mode control logic that mediate the switching process to prevent direct glitch propagation to the output.
2Reliability
If relative timing of switching is maintained to prevent truncation, then output signal quality is improved, but device complexity increases due to difficult timing control
Solution Approach 1:
The patent implements self-service through automatic signal loss detection and autonomous switching mode selection. The system monitors its own input signals, automatically detects loss conditions, and independently switches between timing modes without external intervention, eliminating the need for complex external timing control mechanisms.
Solution Approach 2:
The patent employs feedback mechanisms where the signal loss detection circuitry continuously monitors input clock signals and feeds back status information to the switching mode control. This feedback loop enables automatic adjustment of switching behavior based on real-time signal conditions, replacing complex open-loop timing control.
3Adaptability or versatility
If input signals stop and start at unknown times, then adaptability is improved, but glitches occur due to unknown timing of signal transitions
Solution Approach 1:
The patent applies dynamics by implementing multiple switching modes that can dynamically adapt to different signal conditions. The system transitions between different operational modes (e.g., normal switching, signal loss recovery, reset sequences) based on real-time detection of input signal states, enabling it to handle unknown transition times without producing glitches.
Data Source
AI summary
A digital signal multiplexor and multiplexing method are provided with which switching between different input signals is achieved without producing glitches in the output signal, even in the event of one or more of the input signals stopping and starting at unknown times.