Multiplication Circuit Reuse for FFT and NTT Homomorphic Encryption
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing computation devices for homomorphic encryption require large chip areas due to the need to support both fast Fourier transform and number theoretic transform, which are complex operations, limiting their market applicability.
Innovation Solution
A multiplication unit utilizing a multiplexer to efficiently perform complex number and modulus multiplications, reducing hardware requirements by reusing multipliers for different modes of operation, thereby supporting various homomorphic encryption algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the computation device supports both fast Fourier transform and number theoretic transform operations, then it can process different types of homomorphic encryption ciphertext, but the chip area becomes large
Solution Approach 1:
The multiplication unit is designed to perform multiple functions by switching between complex number multiplication mode and modulus multiplication mode. The same hardware circuit can execute both fast Fourier transform (requiring complex number multiplication) and number theoretic transform (requiring modulus multiplication) operations, eliminating the need for separate dedicated circuits for each operation type.
Solution Approach 2:
The multiplication unit dynamically switches its operation mode based on the input data type and computational requirements. A mode selection mechanism allows the circuit to adapt between complex number arithmetic and modular arithmetic, enabling the same hardware to serve multiple cryptographic algorithms with different mathematical requirements.
2Productivity
If separate hardware circuits are provided for fast Fourier transform and number theoretic transform, then both operations can be performed simultaneously, but the device complexity increases
Solution Approach 1:
The multiplication unit serves as a universal computational engine that can perform both complex number multiplication and modulus multiplication. By using a single multi-functional unit rather than separate dedicated circuits, the device complexity is reduced while maintaining the capability to execute both fast Fourier transform and number theoretic transform operations.
Solution Approach 2:
The patent merges the functionality of separate complex number multiplication circuits and modulus multiplication circuits into a single unified multiplication unit. This consolidation reduces the overall circuit complexity and hardware resource requirements while preserving the computational capabilities needed for both transform types.
3Reliability
If dedicated multipliers are provided for complex number multiplication and modulus multiplication, then both operations can be performed efficiently, but the hardware utilization rate decreases
Solution Approach 1:
The multiplication unit is designed as a universal processor that can efficiently execute both complex number multiplication and modulus multiplication operations. The same hardware resources are dynamically allocated to different computational tasks based on the current operation requirements, maximizing hardware utilization while maintaining computational accuracy for both operation types.
Solution Approach 2:
The multiplication unit maintains continuous useful action by switching between different operation modes without requiring idle dedicated circuits. When one type of multiplication is not needed, the hardware resources are immediately reallocated to the other operation type, ensuring continuous productive use of computational resources.
Data Source
AI summary
A multiplication unit includes first, second, third and fourth receiving terminals, arithmetic units and multiplexers. In complex number mode, the first and second receiving terminals receive a real part value and an imaginary part value of a first complex number, respectively, whereas the third and fourth receiving terminals receive a real part value and an imaginary part value of a second complex number, respectively. In modulus mode, the first and third receiving terminals receive first and second integers, respectively. The multiplexers gate the arithmetic units to perform a complex number multiplication operation according to the first and second complex numbers to generate a third complex number in complex number mode and perform a modulus multiplication operation according to the first and second integers and a predetermined modulus to generate a third integer in modulus mode.