Multiplication Circuitry with Shared Booth Encoding and Independent Adder Arrays

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Solution Overview

Problem

Current processor designs for multiplication operations face challenges in balancing processing performance and energy efficiency due to the lack of efficient hardware circuit logic implementation, particularly in how adder arrays are controlled and Booth encoding is managed.

Innovation Solution

The implementation of a multiplication circuitry with separate adder arrays, each with independent enable control signals, and shared Booth encoding circuitry to reduce circuit area and power consumption by enabling only necessary arrays for specific data element size configurations, allowing for efficient partial product selection and addition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple adder arrays are provided for different data element size configurations, then processing performance and versatility are improved, but circuit area and power consumption increase

Engineering Contradiction:

Improveprocessing performanceVSAvoidcircuit area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

Multiple adder arrays are merged into a single shared adder array that is dynamically reconfigured for different data element size configurations. The adder array can be programmed to function as 8-bit, 16-bit, 32-bit, or 64-bit adder based on control signals, eliminating the need for separate dedicated adder arrays for each configuration and significantly reducing circuit area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The adder array transitions from static dedicated structures to a dynamic reconfigurable structure. Control logic dynamically configures the adder array's operation based on the required data element size, allowing the same hardware to adapt its behavior and width to match the current computational requirements, thus optimizing both area utilization and processing performance.

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

If multiple adder arrays are provided for different data element size configurations, then adaptability is improved, but power consumption increases

Engineering Contradiction:

Improvedata element size configuration supportVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The adder array is designed as a universal multi-functional unit that can perform addition operations for multiple data element size configurations (8-bit, 16-bit, 32-bit, 64-bit) using the same hardware resources. Control logic configures the adder array's behavior based on the required operation, allowing one structure to serve multiple purposes and reducing overall power consumption compared to having separate dedicated arrays.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If separate Booth encoding circuitry is provided for each adder array, then processing performance is improved, but circuit area and power consumption increase

Engineering Contradiction:

Improveprocessing performanceVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

Separate Booth encoding circuitries for each adder array are merged into a single shared Booth encoding circuit that serves all adder arrays. The encoding circuit generates partial product selection indicators that are multiplexed to control the single adder array, reducing the total amount of encoding logic required and lowering power consumption while maintaining processing performance through efficient resource sharing.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

A multiplexer acts as an intermediary between the shared Booth encoding circuit and the adder array. The multiplexer routes the appropriate partial product selection indicators from the encoding circuit to the adder array based on the current data element size configuration, enabling efficient resource sharing while maintaining the functional relationship between encoding and addition operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20240329932A1Multiplication circuitry, apparatus, system, chip-containing product, method and computer-readable medium

Publication Date: 2024.10.03 ARM LTD

AI summary

Multiplication circuitry comprises at least two adder arrays each to add a respective set—of partial products to generate a respective product representing value representing a result of multiplication of a respective pair of portions of bits selected from first and second operands. The adder arrays comprise separate instances of hardware circuitry having at least two separate enable control signals for independently controlling whether at least two subsets of adder arrays are enabled or disabled. Booth encoding circuitry is shared between the adder arrays, to Booth encode the first operand to generate partial product selection indicators each corresponding to a Booth encoding of a respective Booth digit of the first operand. At least two adder arrays operate on respective partial products selected by partial product selection circuitry based on a same partial product selection indicator generated by the shared Booth encoding circuitry based on a same Booth digit of the first operand.