Multiplicative Division Circuit Area Reduction
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Solution Overview
Problem
Conventional division circuits, such as those using the Newton-Raphson and Goldschmidt methods, require full-precision multiplications, leading to large area consumption and inefficiency in hardware resources, especially in combinational dividers.
Innovation Solution
The implementation of a multiplicative division circuit with a lookup table and multiplier circuits that use small-precision multipliers and a squaring circuit, reducing the number of intermediate partial products and precision requirements, allowing for quadratic convergence while minimizing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional Newton-Raphson and Goldschmidt methods are used with full-precision operands, then quadratic convergence and high performance are achieved, but large area consumption occurs
Solution Approach 1:
The patent segments the multiplication process by using a lookup table to provide initial approximations of reciprocal values, thereby breaking down the full-precision multiplication into smaller segments. This allows the circuit to achieve quadratic convergence without requiring complete full-precision operands throughout the entire computation process, thus reducing the area consumption while maintaining performance.
Solution Approach 2:
The patent changes the precision parameter dynamically during the computation process. Instead of using fixed full-precision operands throughout, the circuit uses varying precision levels - starting with lower precision approximations from the lookup table and progressively refining to full precision only where necessary. This parameter change enables area reduction while preserving the quadratic convergence property.
2Adaptability or versatility
If squaring circuit is designed to multiply any two unequal numbers, then general multiplication capability is achieved, but area consumption increases
Solution Approach 1:
The patent applies local quality by designing the squaring circuit with specialized architecture optimized specifically for multiplying a number by itself, rather than creating a universal multiplier that can handle any two numbers. This localized optimization reduces the circuit area by eliminating unnecessary components needed for general multiplication, while the lookup table and other circuits provide the necessary versatility for different multiplication scenarios.
Data Source
AI summary
The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number.