Multiplier Array Operand Rearrangement for Multiply-Accumulate
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Solution Overview
Problem
Existing data processing technologies face inefficiencies in performing multiply-and-accumulate-products (MAP) instructions, requiring additional adders that increase circuit area and latency, especially in digital signal processing applications like FFTs and DCTs.
Innovation Solution
The technique reuses the existing L×M multiplier array by rearranging operands to allow existing adders to accumulate multiple partial products within the array, eliminating the need for additional adders and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional adders are used to perform MAP instructions, then the functionality to accumulate multiple products is improved, but the circuit area and latency increase
Solution Approach 1:
The existing multiplier array is designed to perform both standard multiplication and MAP operations by reconfiguring the same hardware resources. The instruction decoder detects MAP instructions and reuses the existing adders for accumulating multiple partial products, making the multiplier array universal that can handle both regular multiplication and accumulate multiple products operations without requiring dedicated additional adder circuits
Solution Approach 2:
The patent merges the functionality of separate multiplication and accumulation operations into a single unified operation. By rearranging operands and reusing the existing adder array, the MAP instruction combines multiple multiply-accumulate operations into one instruction cycle, effectively merging what would traditionally require separate functional units into a single integrated operation
2Adaptability or versatility
If additional adders are used to perform MAP instructions, then the capability to handle complex operations is improved, but the processing latency increases
Solution Approach 1:
The instruction decoder performs preliminary detection and identification of MAP instructions before execution. By detecting the MAP instruction format in advance and preparing the operand rearrangement, the system can immediately reuse the existing adder array without waiting for additional circuits to be configured, thereby reducing the overall processing latency
Solution Approach 2:
The patent changes the operational parameters of the existing adder array by reconfiguring how operands are arranged and fed into the multiplier. By transforming the input operands into a specific arrangement that aligns with the adder array's existing structure, the system enables the adders to perform accumulation functions without any physical modification, thus avoiding the latency that would result from additional hardware configuration
3Area of stationary object
If the multiplier array is reused for MAP instructions by rearranging operands, then the circuit area is reduced, but the complexity of operand rearrangement increases
Solution Approach 1:
The instruction decoder acts as an intermediary that translates MAP instructions into appropriate operand arrangements for the existing multiplier array. Rather than requiring complex physical reconfiguration of the hardware, the decoder mediates between the high-level MAP instruction and the low-level hardware operations, automatically handling the operand rearrangement through control logic that selects and prepares operands in the required format
4Ease of operation
If standard multiply instructions are maintained, then the simplicity of operation is preserved, but the efficiency for accumulate multiple products operations is limited
Solution Approach 1:
The multiplier array is designed with universal functionality that allows it to execute both simple standard multiply instructions and complex MAP instructions using the same hardware resources. The instruction decoder identifies MAP instructions and reuses the existing adder array for accumulating multiple partial products, enabling the system to maintain operational simplicity while significantly improving productivity for accumulate multiple products operations
Data Source
AI summary
An apparatus has processing circuitry comprising an L×M multiplier array. An instruction decoder associated with the processing circuitry supports a multiply-and-accumulate-product (MAP) instruction for generating at least one result element corresponding to a sum of respective E×F products of E-bit and F-bit portions of J-bit and K-bit operands respectively, where 1<E<J≤L and 1<F<K≤M. In response to the MAP instruction, the instruction decoder controls the processing circuitry to rearrange F-bit portions of the second K-bit operand to form a transformed K-bit operand, and to control the L×M multiplier array in dependence on the first J-bit operand and the transformed K-bit operand to add the respective E×F products using a subset of the adders used for accumulating partial products for a conventional multiplication.