Multiplier With Built-In Accumulator Circuit
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Solution Overview
Problem
Lower-end digital signal processing (DSP) devices lack a built-in accumulator, necessitating the use of external resources for accumulation, leading to slower calculation speeds.
Innovation Solution
Incorporating a built-in accumulator within the multiplier block, utilizing a logic circuit to generate partial products, a block of adders to sum these products, and a 3:2 adder to generate intermediate values stored in an accumulator, allowing for efficient multiplication and accumulation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If external resources are used for accumulation in lower-end DSP devices, then the device can perform accumulation functions, but the calculation speed becomes slower
Solution Approach 1:
The patent combines the accumulator function with the multiplier block by integrating an adder and accumulator circuit within the multiplier structure. This merging allows the device to perform both multiplication and accumulation operations using a unified circuit, thereby improving calculation speed without significantly increasing overall device complexity.
Solution Approach 2:
The multiplier block is designed to perform multiple functions including multiplication, accumulation, and multiplication followed by addition. By making the multiplier block universal and capable of handling different operation modes, the patent eliminates the need for separate accumulation resources, thus improving productivity while maintaining acceptable device complexity.
2Productivity
If memory blocks are used as look-up tables to store multiplication results, then accumulation can be performed, but the calculation speed decreases
Solution Approach 1:
The patent replaces the memory-based look-up table approach with a direct computational approach using an adder and accumulator circuit. Instead of storing multiplication results in memory and retrieving them, the system performs real-time addition of partial products, thereby eliminating the speed bottleneck associated with memory access while maintaining manufacturing simplicity.
3Productivity
If a built-in accumulator is integrated within the multiplier block, then calculation speed improves, but the multiplier block complexity increases
Solution Approach 1:
The patent merges the accumulator functionality into the multiplier block by integrating an adder circuit that processes partial products directly within the multiplier structure. This consolidation improves calculation speed by eliminating data transfer between separate blocks, while the shared resources and integrated design minimize the increase in overall complexity.
Data Source
AI summary
Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.