Reduced-Width Multiplier Carry Estimation Circuit
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Solution Overview
Problem
Existing multipliers face challenges in reducing computational complexity and effectively compensating for truncation errors, particularly when using different partial product generating methods, as existing error compensation methods are not applicable across various types of multipliers and lack detailed analysis for system-level analysis.
Innovation Solution
A method for a low-error reduced-width multiplier that dynamically generates compensation terms using a compensating circuit to estimate carry values, applicable to both Baugh-Wooly and Booth-encoded multipliers, by processing input values and associating partial products into most and least significant parts to reduce computational complexity and compensate for truncation errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If direct-truncated multiplier is used to reduce computational complexity, then computation burden is reduced, but truncation error increases significantly
Solution Approach 1:
The patent introduces a compensating circuit as an intermediary component that generates compensation terms to correct the truncation error. This mediator bridges the gap between the simplified direct-truncated multiplier and the accurate full-precision result, allowing the system to benefit from reduced computational complexity while maintaining measurement precision through error compensation.
Solution Approach 2:
The compensating circuit performs preliminary analysis of the truncated partial products to predict and generate compensation terms before the final summation. By anticipating the truncation error and preparing correction values in advance, the system can apply the compensation terms to restore accuracy without increasing the fundamental computational complexity of the truncated multiplier.
2Measurement precision
If existing error compensation methods are applied, then truncation error is reduced, but device complexity increases and applicability is limited to specific multiplier types
Solution Approach 1:
The patent designs a universal compensating circuit that can be applied to multiple types of multipliers including Baugh-Wooly and Booth-encoded multipliers. The circuit performs multiple functions: analyzing truncated partial products, generating compensation terms, and correcting errors across different multiplier architectures. This multi-functional design reduces device complexity by eliminating the need for separate compensation mechanisms for each multiplier type.
Solution Approach 2:
The compensating circuit adapts to different multiplier types by changing its analysis parameters and compensation term generation logic based on the specific partial product structure. By dynamically adjusting parameters such as the weighting factors and compensation coefficients according to the multiplier type, the circuit maintains low complexity while achieving accurate error compensation across various architectures.
3Productivity
If Baugh-Wooly or Booth encoding is used for partial product generation, then multiplication efficiency is improved, but error compensation becomes difficult with existing methods
Solution Approach 1:
The patent implements a dynamic compensating circuit that adapts its operation based on the type of partial product encoding used. The circuit dynamically adjusts its analysis method and compensation term generation strategy according to whether Baugh-Wooly or Booth encoding is employed. This dynamic adaptability allows the system to maintain high multiplication efficiency while achieving effective error compensation for each specific encoding type.
Data Source
AI summary
A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.