Multiplier Circuit Array for Flexible Data Precision
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Solution Overview
Problem
Current integrated circuits lack an efficient and flexible solution for performing multiply operations across different data formats and precisions, particularly in multiplier-accumulator circuits, which limits their ability to process data effectively in various applications such as image filtering.
Innovation Solution
A multiplier circuit array comprising interconnected multiplier circuits that can perform multiply operations across different data formats and precisions, including floating point and integer types, with each circuit configured to handle specific portions of the operation, such as sign, exponent, and fraction fields, and interconnected via buses for data combination and rounding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single multiplier circuit is used, then the device complexity is low, but the adaptability to different data formats and precisions is limited
Solution Approach 1:
The multiplier circuit is divided into multiple specialized multiplier circuits, each configured to handle specific data formats and precisions (e.g., first multiplier circuit for one format, second for another). This segmentation allows the system to support multiple formats without requiring a single complex reconfigurable circuit, as each segment is optimized for its specific function.
Solution Approach 2:
The plurality of multiplier circuits collectively provide universal support for multiple data formats and precisions. By having multiple circuits that can be selectively activated based on the input data format, the system achieves multi-functionality at the system level while keeping individual circuits relatively simple and specialized.
2Productivity
If multiple specialized multiplier circuits are used, then the processing speed and precision are improved, but the device complexity increases
Solution Approach 1:
The processing function is segmented across multiple specialized multiplier circuits, allowing parallel or selective execution based on data format requirements. This segmentation enables the system to achieve high processing speed for specific formats by using circuits optimized for those formats, while maintaining manageable complexity through specialization.
Solution Approach 2:
Each multiplier circuit is designed with local quality optimized for its specific data format and precision requirement. This means each circuit has the specific structural characteristics needed for its designated format, enabling high-performance processing for that format while avoiding the overhead of supporting all formats in a single circuit.
3Adaptability or versatility
If a fixed-precision multiplier circuit is used, then the manufacturing precision is high, but the adaptability to different precisions is poor
Solution Approach 1:
The system segments the precision handling function across multiple multiplier circuits, with each circuit fixed-optimized for a specific precision level. This allows the system to adapt to different precision requirements by selecting the appropriate circuit, while each individual circuit maintains high manufacturing precision for its designated precision level.
Data Source
AI summary
An integrated circuit comprising a MAC pipeline including a plurality of MACs connected in series to perform concatenated multiply and accumulate operations, wherein each MAC includes a multiplier circuit array, including a plurality of multiplier circuits, to multiply first data and weight data and generate product data. The plurality of multiplier circuits, in one embodiment, includes a first multiplier circuit to multiply first portions of the first data and the weight data to generate a first field, and a second multiplier circuit to multiply a second portions of the first data and weight data to generate a second field, wherein the product data includes data which is representative of the first field and the second field. An accumulator circuit adds the product data, output from the associated multiplier circuit array, and second data. The multiply cores of the first and second multiplier circuits are separate and different.