1/3 Multiplier Circuit for H.264 CABAC Calculation
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Solution Overview
Problem
The H.264 compression coding format requires derivation of a CABAC_ZERO_WORD, which is typically calculated using software, consuming significant CPU processing power and limiting frame rates and network compatibility, especially for CPUs with low processing speed.
Innovation Solution
An image processor employing a ⅓ multiplier circuit with a loop operation circuit and a setting circuit to perform high-speed hardware calculation of the CABAC_ZERO_WORD, using a simplified circuit configuration that includes a bit shift circuit and an adder circuit to achieve accurate and efficient ⅓ multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the CABAC_ZERO_WORD is calculated with a software program, then the calculation conforms to the H.264 standard algorithm, but the CPU processing power is occupied causing elongated generation time for NAL unit packets
Solution Approach 1:
The patent replaces the software-based calculation system with a dedicated hardware circuit system. The 1/3 multiplier circuit implements the CABAC_ZERO_WORD calculation using hardware components (multiplier circuit, adder circuit, bit shift circuit) instead of software programs, thereby eliminating CPU occupation and significantly improving processing speed while maintaining calculation accuracy according to the H.264 standard algorithm
Solution Approach 2:
The patent extracts the CABAC_ZERO_WORD calculation function from the general-purpose CPU software execution and isolates it into a dedicated hardware circuit module. This extraction allows the calculation to be performed independently in hardware, removing the burden from the CPU and enabling parallel operation, thus improving both processing speed and system efficiency
2Measurement precision
If multiple bit shift circuits and multiple adders are connected in parallel to perform 1/3 multiplication, then the calculation accuracy is improved, but the circuit configuration becomes complex
Solution Approach 1:
The patent employs a dynamic loop structure where a single bit shift circuit and a single adder circuit are reused iteratively N times through a loop control mechanism. This dynamic approach replaces the static parallel configuration of multiple circuits, achieving the same calculation accuracy through sequential reuse of components, thereby significantly reducing circuit complexity while maintaining precision
Solution Approach 2:
The patent merges multiple identical calculation functions into a single iterative loop structure. Instead of having separate bit shift circuits and adders operating in parallel, the patent combines their functions into one reusable set of circuits that perform the same operation repeatedly through the loop, reducing the total number of components while achieving equivalent computational results
3Device complexity
If a fixed number of bit shift circuits are connected in parallel, then the circuit configuration is simple, but the 1/3 multiplication may lack accuracy or perform excessive operations
Solution Approach 1:
The patent introduces a dynamic loop control mechanism that adjusts the number of iterations N based on the input value characteristics. This dynamic approach allows the circuit to perform the minimum necessary operations for accurate 1/3 multiplication without excessive iterations, optimizing both accuracy and efficiency while maintaining a relatively simple circuit structure compared to fixed parallel configurations
Solution Approach 2:
The patent changes the operational parameter (number of iterations N) dynamically based on the input value and required precision. By adjusting N according to the specific calculation needs, the system achieves accurate 1/3 multiplication without performing unnecessary operations, thereby maintaining simplicity while ensuring precision
Data Source
AI summary
The image processor includes a ⅓ multiplier circuit that approximately multiplies an input value X by ⅓. The ⅓ multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input value, a bit shift circuit that performs bit shift by 2 bits to the right on a value output from the register, and an adder circuit that adds an input value and a value output from the bit shift circuit, and inputs the added value to the register.