Programmable Multiplier Decomposition for Area Reduction
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Solution Overview
Problem
Existing programmable integrated circuit devices require a large number of multipliers to perform larger multiplication operations, which is area-intensive and inefficient.
Innovation Solution
The use of ternary and binary decompositions to reduce the number of multipliers required for large multiplications, such as 54-by-54 and 36-by-36 multiplications, by splitting operands into smaller parts and using fewer multipliers with additional adders and shifters to achieve the same result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If linear decomposition is used to perform large multiplications using smaller multipliers, then the multiplication capability is achieved, but the number of multipliers required increases significantly and device area is consumed
Solution Approach 1:
The patent segments large multiplication operations into smaller sub-multiplications using binary and ternary decomposition methods. For example, a 54-by-54 multiplication is divided into multiple 18-by-18 sub-multiplications, where operands are split into smaller parts that can be processed by available multiplier resources. This segmentation enables the system to achieve large multiplication capability while using fewer physical multipliers by strategically organizing and combining results from multiple smaller operations.
2Productivity
If more multipliers are used to perform large multiplications, then computation speed is improved, but device area and resource consumption increase
Solution Approach 1:
The patent implements dynamic resource allocation and configuration where the same set of multipliers can be dynamically reconfigured to perform different multiplication sizes and types. The system adapts the number and size of active multipliers based on the specific computation requirements, allowing efficient utilization of fixed hardware resources. This dynamic approach enables the device to maintain high computation speed for various multiplication operations without requiring dedicated multipliers for each operation size.
3Area of stationary object
If ternary decomposition is used to reduce the number of multipliers, then device area is reduced, but additional adders and computational complexity are required
Solution Approach 1:
The patent employs parameter changes by switching between different decomposition strategies (binary vs. ternary) and multiplier configurations based on the specific computation requirements. The system can change the operational parameters such as the number of multipliers active, the decomposition method used, and the organization of partial products to optimize for either area efficiency or computational simplicity depending on the application context. This flexibility allows the same hardware to efficiently handle different multiplication scenarios.
Data Source
AI summary
A specialized processing block is configurable as one ternary linear decomposition or two binary linear decompositions to perform large multiplications using smaller multipliers, and includes a first number of multiplier circuits of a first size, a second number of pre-adders, and a third number of block inputs. The block inputs are connected to a first subset of the multiplier circuits, and to the pre-adders which are connected to a second subset of the multiplier circuits. There is also a fourth number of additional inputs. A plurality of shifters shift partial product outputs of each of the multipliers by various shift amounts. A joint adder structure combines the shifted partial products. Controllable elements controllably select between different configurations of inputs to the multipliers and pre-adders, controllably connect and disconnect certain ones of the shifted partial products, and selectively split the joint adder structure into two smaller adder structures.