Formal Verification of Multiplier Circuit Designs
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Solution Overview
Problem
Formal verification of arithmetic circuits, particularly multipliers, is challenging due to the lack of robust frameworks for satisfiability and decision diagrams, leading to difficulties in ensuring functional correctness, especially in full-custom designs where manual optimizations result in complex structures that are hard to abstract beyond the Boolean bit-level, and standard property checking often fails for designs with different architectures.
Innovation Solution
A method and system for formal verification of arithmetic circuits using a Booth encoding-based approach, where a reference design is created at the word level with a partial product generator and adder tree, allowing for equivalence checking between the reference and actual circuit designs, and extracting an adder network to verify the arithmetic functions, facilitating automatic proof frameworks and correcting designs through bit-level reasoning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If standard property checking is used for multiplier verification, then verification process is simple, but verification fails for designs with different architectures
Solution Approach 1:
The patent introduces an intermediary representation layer between the circuit netlist and the verification engine. This intermediary form represents arithmetic operations in a standardized way that can be verified regardless of the specific architectural implementation details, allowing different multiplier architectures to be verified through a common verification framework
2Reliability
If equivalence checking is used to verify multipliers, then verification can work across different architectures, but the process becomes computationally expensive and complex
Solution Approach 1:
The verification process is segmented into distinct phases: first converting the netlist to an intermediate representation, then performing verification on this simplified representation. This segmentation reduces the complexity of the overall verification process by breaking down the complex equivalence checking into more manageable steps
3Speed
If manual optimization is applied to meet timing requirements, then circuit performance is improved, but design complexity increases and abstraction becomes difficult
Solution Approach 1:
The patent creates a copy of the optimized circuit in an intermediate representation that preserves the essential arithmetic functionality while stripping away the complex optimization details. This copy can be verified using standard techniques without requiring the verifier to understand or process the complex manual optimizations that were applied to the original circuit
4Loss of information
If BDDs are used to represent multiplier outputs, then Boolean function representation is achieved, but node explosion occurs leading to memory exhaustion
Solution Approach 1:
The patent changes the representation parameter from traditional BDDs to a novel intermediate representation that uses a different data structure and organization principle. This new representation achieves compact encoding of arithmetic functions without the exponential node growth that plagues conventional BDD approaches
Data Source
AI summary
A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification.