Multiplier-less Neural Processing Unit for Low Power Convolution
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Solution Overview
Problem
Neural processing units (NPUs) face high power consumption and gate count due to the presence of multipliers in MAC units, which are inefficient in computing convolutional neural networks (CNNs) as they waste power on zero bits and experience bit-toggling from small-magnitude values.
Innovation Solution
The method decomposes each weight into multiple sub-weights with only one valid bit, allowing for bit-plane processing that replaces multiplications with shifts and accumulations, reducing power consumption by eliminating unnecessary multiplications and bit-toggling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If MAC units with multipliers are used for convolution calculations, then computation accuracy is maintained, but power consumption and gate count increase significantly
Solution Approach 1:
The patent segments the weight values into multiple bit-planes, where each bit-plane contains only bits at the same significance position from multiple weights. This segmentation allows the convolution operation to be decomposed into multiple simpler operations that process one bit-plane at a time, replacing full multipliers with simpler adder trees that operate on segmented data.
Solution Approach 2:
The patent transforms the traditional weight-space computation into a bit-plane dimension. Instead of processing weights directly in their original form, it reorganizes weights by bit significance positions across different weights, creating bit-plane matrices. This dimensional transformation enables the use of addition-based computation instead of multiplication, reducing power consumption while maintaining accuracy.
2Productivity
If MAC units with multipliers are used for convolution calculations, then computation speed is maintained, but gate count increases significantly
Solution Approach 1:
The patent segments the weight values into multiple bit-planes, where each bit-plane contains only bits at the same significance position from multiple weights. This segmentation allows the convolution operation to be decomposed into multiple simpler operations that process one bit-plane at a time, replacing full multipliers with simpler adder trees that operate on segmented data.
Solution Approach 2:
The patent extracts only the significant bits from weight values and organizes them into bit-plane matrices. By taking out and reorganizing the essential computational information into a compact bit-plane format, the system eliminates the need for complex multiplier circuits while preserving the necessary computation capability through addition-based operations.
3Reliability
If traditional multiplication-based MAC operations are used, then computational completeness is achieved, but unnecessary power is consumed on zero bits
Solution Approach 1:
The patent extracts only the significant bits from weight values and organizes them into bit-plane matrices. By taking out and reorganizing the essential computational information into a compact bit-plane format, the system eliminates the need for complex multiplier circuits while preserving the necessary computation capability through addition-based operations.
Solution Approach 2:
The patent performs computation on only the necessary bit-planes that contain significant information, rather than processing all bits uniformly. By identifying and processing only the relevant bit-planes (those with non-zero values), the system avoids wasting power on zero bits while maintaining complete computational accuracy for the convolution operation.
Data Source
AI summary
A method for convolution calculation in a neural network is provided. The method comprises: decomposing each weight into multiple sub-weights, each with only one valid bit, representing different bit significance (bit plane); accumulating input feature map units corresponding to each of the sub-weights with the same bit significance to obtain intermediate sums; shifting each of the intermediate sums according to the bit significance of the corresponding sub-weights to obtain shifted intermediate sums; and accumulating the shifted intermediate sums.