Digital Multiplier Error Detection via Logarithmic Checking
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Solution Overview
Problem
Existing methods for detecting transient and permanent errors in digital multipliers or squaring units, such as redundancy, parity checking, and residue code checking, are inefficient in recognizing small percentage errors due to high hardware and time requirements or limitations in detecting multi-bit errors.
Innovation Solution
A method using logarithmic checking, specifically the Mitchell approximation for calculating log 2 values, determines an error signal by forming the difference between the sum and product logarithms of the factors in a multiplication operation, allowing for the diagnosis of correctness within specified percentage limits, employing a difference formation unit, logarithm formation units, and normalizing units to approximate mantissas to reduce precision and increase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy methods are used to secure multipliers, then error detection capability is improved, but hardware and time outlay increases significantly
Solution Approach 1:
The patent changes the parameter of error detection from direct result comparison (redundancy) to logarithmic domain comparison. By transforming the multiplication verification into a logarithmic operation where log(a*b) = log(a) + log(b), the system achieves error detection with significantly reduced hardware complexity while maintaining reliability.
Solution Approach 2:
The patent replaces the mechanical redundancy approach (multiple multipliers and comparators) with a logarithmic checking mechanism. This substitution uses the mathematical property of logarithms to simplify the verification process, reducing the need for complex hardware structures while preserving error detection capability.
2Device complexity
If parity checking is used, then hardware requirements are reduced, but detection of multi-bit errors becomes unreliable
Solution Approach 1:
The patent transitions from parity bit checking to logarithmic domain verification. This parameter change enables the system to detect multi-bit errors effectively by comparing logarithmic values, where even small errors in the product manifest as detectable deviations in the logarithmic domain, thus improving reliability without significantly increasing hardware complexity.
3Productivity
If approximation methods are used for log 2 calculation, then computation speed is improved, but precision of error detection decreases
Solution Approach 1:
The patent implements a feedback mechanism where the approximate logarithmic calculation results are compared against expected values. The system uses the difference between calculated and expected logarithmic values to detect errors, and the approximation error itself serves as a reference for determining when a deviation indicates a actual multiplication error versus normal approximation variance.
Data Source
AI summary
A method for calculating an error signal that enables a diagnosis of the correctness of a product, determined by a first multiplier unit, of a first factor and a second factor, the error signal being determined by a difference formation unit as the difference of a sum logarithm and a product logarithm.