Floating Point Multiplier Power Optimization via Partial Product Deactivation
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Solution Overview
Problem
Existing configurable specialized processing blocks in programmable integrated circuits consume more power than necessary, particularly in floating point multipliers, which can be optimized for reduced precision operations without compromising performance significantly.
Innovation Solution
Incorporating a first and second multiplier with switching circuitry to deactivate the first multiplier, a compressor tree to combine partial products, and truncating circuitry to set least significant bits to zero, along with logic gates to selectively zero outputs, thereby reducing power consumption while maintaining acceptable precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a full-precision floating point multiplier is used, then calculation precision is maintained, but power consumption increases
Solution Approach 1:
The floating point multiplier is divided into multiple smaller multipliers (first multiplier, second multiplier, third multiplier) that process different bit segments of the input operands. Each multiplier handles a specific range of bit positions, and their partial products are combined through addition to produce the final result. This segmentation allows selective activation of multipliers based on precision requirements, reducing power consumption when full precision is not needed.
Solution Approach 2:
The system dynamically changes the precision parameter by selectively activating or deactivating specific multipliers based on the required output precision. When lower precision is acceptable, the first multiplier (handling less significant bits) can be deactivated, reducing the number of active computational units and thereby reducing power consumption while still providing acceptable calculation results for the application.
2Measurement precision
If all multipliers are activated, then full precision results are achieved, but device complexity increases
Solution Approach 1:
The system implements dynamic configuration of the multiplier array, where the activation state of individual multipliers can be changed based on runtime requirements. Control logic selectively enables or disables the first multiplier depending on whether full precision is required, allowing the device to adapt its complexity level to match the actual computational needs, thus avoiding unnecessary complexity when full precision is not required.
3Use of energy by moving object
If the first multiplier is deactivated, then power consumption is reduced, but calculation precision decreases
Solution Approach 1:
The system performs partial multiplication by deactivating the first multiplier that handles the least significant bit segments. This partial action is sufficient for applications that tolerate imprecision in the lower bits, achieving acceptable power reduction while maintaining adequate precision for the specific application requirements. The trade-off is explicitly designed to allow imprecision in less critical bit positions.
Data Source
AI summary
Systems and methods are described herein for reducing an amount of power consumption in a programmable integrated circuit device configured to perform a multiplication operation. The device includes a first multiplier that generates a first partial product associated with a first set of bit locations and a second multiplier that generates a second partial product associated with a second set of bit locations that are more significant than the first set of bit locations. The device further includes a switching circuitry to deactivate the first multiplier to reduce an amount of power consumed by the programmable integrated circuit device.