Multiplier Circuitry Shift Instruction via Operand Rearrangement
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Solution Overview
Problem
Existing data processing technologies face inefficiencies in performing multiply-and-accumulate operations, requiring additional adders that increase circuit area and latency, especially in digital signal processing applications like FFTs and DCTs.
Innovation Solution
The technique reuses the existing multiplier array by rearranging operands to allow the adders to accumulate multiple partial products within the array, eliminating the need for additional adders and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If additional adders are used to perform multiply-and-accumulate operations, then processing capability is improved, but circuit area increases
Solution Approach 1:
The existing multiplier array is made multi-functional by enabling it to perform both multiplication and accumulation operations. The same multiplier circuitry that multiplies input operands is also used to accumulate partial products, eliminating the need for separate adder circuits. This is achieved by controlling the multiplier to selectively accumulate partial products based on instruction type.
2Productivity
If additional adders are used to perform multiply-and-accumulate operations, then processing capability is improved, but latency increases
Solution Approach 1:
The accumulation function is merged into the existing multiplier circuitry rather than being implemented as a separate addition stage. By combining the multiplication and accumulation functions in a single circuit unit, the patent eliminates the sequential dependency that would otherwise require additional time for carry propagation through separate adder chains, thereby reducing latency.
3Measurement precision
If dedicated multiplier circuitry is used for shift operations, then shift precision is improved, but device complexity increases
Solution Approach 1:
The multiplier circuitry is configured to perform multiple functions including both multiplication and shift operations. By using the same circuit for different operations, the patent avoids increasing device complexity while maintaining precision through controlled accumulation of partial products that represent shifted values.
Data Source
AI summary
An apparatus has processing circuitry comprising multiplier circuitry for performing multiplication on a pair of input operands. In response to a shift instruction specifying at least one shift amount and a source operand comprising at least one data element, the source operand and a shift operand determined in dependence on the shift amount are provided as input operands to the multiplier circuitry and the multiplier circuitry is controlled to perform at least one multiplication which is equivalent to shifting a corresponding data element of the source operand by a number of bits specified by a corresponding shift amount to generate a shift result value.