Hardware Multiplier Bypassing Zero-Value Multiplications
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Solution Overview
Problem
Existing hardware solutions for neural networks face challenges in achieving high computational performance with low power consumption, particularly in matrix multiplication operations, which are common and computationally intensive, leading to significant power wastage due to zero-result multiplications.
Innovation Solution
A hardware matrix multiplier system that detects zero inputs and bypasses unnecessary multiplications by disabling operand register updates and using a zero-value signal to output a zero result, reducing power consumption and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware multiplication is performed for all operations in neural networks, then computational performance is improved, but power consumption increases due to zero-result multiplications
Solution Approach 1:
The patent extracts and identifies zero-value operands from the multiplication operation before execution. By detecting zero inputs and removing them from the computation pipeline, the system avoids performing unnecessary multiplication operations, thereby reducing power consumption while maintaining computational throughput.
Solution Approach 2:
The patent implements preliminary detection of zero-value operands before the multiplication operation is executed. This preliminary action allows the system to bypass the multiplication unit when zeros are detected, preventing wasted energy consumption on operations that would produce zero results anyway.
2Use of energy by moving object
If zero-value multiplications are bypassed, then power consumption is reduced, but hardware complexity increases due to detection logic
Solution Approach 1:
The patent applies zero-detection logic selectively at specific points in the computation pipeline where operands are available, rather than implementing a complex global control system. This localized approach adds minimal hardware overhead while achieving significant power savings by focusing detection efforts only where necessary.
Solution Approach 2:
The patent introduces a simple intermediary detection mechanism that sits between the input operands and the multiplication unit. This intermediary component detects zero values and generates control signals to bypass the multiplication operation, adding minimal complexity while effectively reducing power consumption.
Data Source
AI summary
A device (e.g., integrated circuit chip) includes a first operand register, a second operand register, a multiplication unit, and a hardware logic component. The first operand register is configured to store a first operand value. The second operand register is configured to store a second operand value. The multiplication unit is configured to at least multiply the first operand value with the second operand value. The hardware logic component is configured to detect whether a zero value is provided and in response to a detection that the zero value is being provided: cause an update of at least the first operand register to be disabled, and cause a result of a multiplication of the first operand value with the second operand value to be a zero-value result.