Multiplierless FIR Filter Architecture for Low-Power Qubit Control
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Solution Overview
Problem
Quantum computing systems are sensitive to environmental influences and have limited capacity to remove heat generated by drive electronics, necessitating efficient and low-power filter solutions for qubit control.
Innovation Solution
Implementing a folded finite impulse response (FIR) filter with an arbitrary coefficient multiplierless design using a series-connected arrangement of unit delays and summers, along with multiplexing stages and coefficient multipliers, to reduce hardware complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional FIR filter implementations are used in quantum computing systems, then filtering functionality is provided, but power consumption increases and heat generation exceeds the limited cooling capacity of the dilution refrigerator
Solution Approach 1:
The patent extracts and eliminates redundant computational operations from the FIR filter implementation. By using a folded architecture with shared multipliers and coefficient reuse, unnecessary calculations are removed, directly reducing power consumption while maintaining the filtering function needed for qubit control
Solution Approach 2:
The patent merges multiple identical multiplier units into a single shared multiplier that is time-multiplexed across different coefficient calculations. This consolidation reduces the total number of active components, lowering power consumption and heat generation while preserving the required filtering functionality through coordinated operation
2Reliability
If high-speed waveform synthesizers are used to maintain proper qubit control phase, then qubit coherence is maintained, but heat generation from drive electronics exceeds the cooling capacity of the dilution refrigerator
Solution Approach 1:
The patent implements periodic action through the folded FIR filter architecture where a single multiplier unit is time-multiplexed to serve multiple coefficient calculations in sequence. This periodic operation maintains the necessary computational throughput for qubit control while allowing the system to operate at lower instantaneous power levels, reducing heat generation below the refrigerator's capacity
Solution Approach 2:
The patent uses coefficient copying and reuse across multiple filter stages. Instead of performing independent multiplications for each coefficient, the same coefficient values are copied and reused in different time slots, reducing the total computational workload and associated heat generation while maintaining accurate qubit control
3Measurement precision
If traditional multiplier-based FIR filters are implemented, then filtering accuracy is achieved, but hardware complexity increases and power consumption rises
Solution Approach 1:
The patent makes the multiplier unit universal by designing it to handle multiple coefficient calculations through time-multiplexing. A single multiplier structure performs the work of what would traditionally require multiple dedicated multipliers, reducing hardware complexity while maintaining filtering accuracy through precise timing and control of the universal unit's operation
Solution Approach 2:
The patent applies preliminary action by pre-calculating and storing coefficient values in memory before they are needed in the filter operation. This allows the complex multiplication operations to be performed efficiently using stored values, reducing the real-time computational complexity while preserving filtering accuracy through the use of pre-prepared coefficient data
Data Source
AI summary
The present disclosure provides implementations of a filter suitable for use in quantum computing systems and other low-power, high-speed applications. In some aspects, a filter circuit includes a series-connected arrangement of unit delays and summers in an alternating pattern. The filter circuit further includes a plurality of coefficient multipliers, each having a respective output connected with one or more of the summers, and each including a multiplexing stage including one or more multiplexers addressed using one or more bits of a respective input coefficient vector. A first coefficient multiplier of the plurality of coefficient multipliers includes a partial product stage configured to provide a plurality of integer partial products of an input data vector to the multiplexing stages of the plurality of coefficient multipliers.