Multiply and Accumulate Feedback Hardware for Polynomial Evaluation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional digital pre-distortion systems for wireless communication devices face significant complexity and processing costs due to the real-time evaluation of polynomials required for linearizing power amplifier gain, which can lead to inefficient power amplifiers and poor signal quality.
Innovation Solution
A system utilizing a single chip digital front end processor with integrated multiply and accumulate feedback hardware to efficiently perform Horner's algorithm for polynomial evaluation, allowing for high throughput and power-efficient digital pre-distortion by pipelining operations and reducing the complexity of polynomial evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional digital pre-distortion systems use polynomial evaluation for linearizing power amplifier gain, then signal quality is improved, but processing complexity and costs increase significantly
Solution Approach 1:
The patent segments the polynomial evaluation process into multiple pipeline stages, where each stage handles a specific portion of the computation. This allows the complex polynomial evaluation to be broken down into manageable segments that can be processed in parallel, reducing overall processing complexity while maintaining signal quality.
Solution Approach 2:
The patent implements preliminary computation of polynomial coefficients and intermediate values in advance, storing them in lookup tables or buffers. This preliminary action allows the main processing stage to use pre-computed values, significantly reducing real-time processing complexity while preserving the accuracy needed for signal quality.
2Reliability
If polynomial evaluation is performed in real-time for digital pre-distortion, then power amplifier linearization is achieved, but processing speed requirements increase complexity
Solution Approach 1:
The patent implements a continuous pipeline architecture where polynomial evaluation, multiplication, and accumulation operations overlap in time. This continuity allows real-time processing to maintain amplifier linearization without requiring peak processing speeds that would increase complexity, as the workload is distributed continuously across multiple stages.
3Productivity
If complex polynomial evaluation is performed with high throughput, then processing efficiency is improved, but hardware complexity increases
Solution Approach 1:
The patent nests multiple computational operations within a hierarchical structure, where inner operations (such as multiplication and accumulation) are embedded within outer operations (polynomial evaluation stages). This nesting allows efficient resource sharing and reuse, achieving high throughput while minimizing the total hardware complexity through systematic resource consolidation.
Data Source
AI summary
A method and apparatus may be used to evaluate a polynomial by initializing a multiply and accumulate feedback apparatus (260) comprising a multiplier stage (264) having an output coupled to an input of an accumulator stage (267) having an accumulator feedback output (269) selectively coupled to an input of the multiplier stage over a plurality of clock cycles; iteratively calculating a final working loop variable z over an additional plurality of clock cycles; multiplying the final working loop variable z and a complex input vector x to compute a final multiplier value; and adding a least significant complex polynomial coefficient to the final multiplier value using the multiplier stage of the multiply and accumulate feedback apparatus to yield a result of the polynomial evaluation.