Multiply-Accumulate Instruction Processing with Shift Flag
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Solution Overview
Problem
In digital signal processing, multiply-accumulate operations often result in overflow, leading to skewed results or increased bit width requirements, which are inefficient and costly, especially in SIMD instructions used in vector digital signal processing.
Innovation Solution
The introduction of a shift flag in the multiply-accumulate instruction allows for right shifting of the multiplication result before accumulation, reducing the risk of overflow without increasing storage costs or bit width, and extending the instruction's applicability to both multiply-accumulate and multiply-subtract operations through a negation flag.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of bits for representing a result is expanded to prevent overflow, then data information loss is prevented, but storage resources increase and operation costs increase
Solution Approach 1:
The patent changes the parameter of bit width dynamically by introducing a shift flag that allows the multiplication result to be right-shifted before accumulation. This enables the system to use fewer bits (e.g., 32-bit accumulation register) while preventing overflow through the shift operation, thereby resolving the contradiction between reliability and storage resource consumption
Solution Approach 2:
The patent introduces dynamic control through the shift flag parameter, which allows the system to adjust the effective bit width of the multiplication result on-the-fly. This dynamic approach enables overflow prevention without permanently expanding storage resources, as the shift amount can be adjusted based on the actual accumulation needs
2Device complexity
If saturation operation is performed on the result, then overflow is handled without expanding bit width, but the overall result may be skewed when actual result far exceeds the range
Solution Approach 1:
Instead of using saturation operation which clamps values to fixed bounds, the patent changes the parameter of the accumulation result representation by introducing a shift flag. This allows the system to right-shift the multiplication result before accumulation, effectively scaling down large values to fit within the available bit width while maintaining proportional accuracy, thus avoiding the skewing effect of saturation
3Reliability
If more bits are used to represent exact operation result, then overflow is prevented, but operation bit width increases and subsequent reduction operations are required
Solution Approach 1:
The patent introduces a shift flag parameter that allows the multiplication result to be right-shifted before accumulation. This enables overflow prevention using standard bit widths (e.g., 32-bit registers) without requiring wider intermediate representations, thereby eliminating the need for subsequent reduction operations and improving operation efficiency
Data Source
AI summary
The present invention discloses an instruction processing apparatus, comprising a first register adapted to store first source data, a second register adapted to store second source data, a third register adapted to store accumulated data, a decoder adapted to receive and decode a multiply-accumulate instruction, and an execution unit. The multiply-accumulate instruction indicates that the first register serves as a first operand, the second register serves as a second operand, the third register serves as a third operand, and a shift flag. The execution unit is coupled to the first register, the second register, the third register, and the decoder, and configured to execute the decoded multiply-accumulate instruction so as to acquire the first source data from the first register and acquire the second source data from the second register, perform a multiplication operation on the first source data and the second source data so as to obtain a multiplication result, shift the multiplication result according to the shift flag, and add the shifted multiplication result and the accumulated data in the third register so as to obtain a multiply-accumulate result. The present invention further discloses a corresponding instruction processing method, a computing system, and a system on chip.