Multiport Cache Memory Bank Contention Reduction
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Solution Overview
Problem
Conventional multiport cache memory systems face high bank contention probabilities during simultaneous reading operations, leading to increased area requirements, power consumption, and reduced operating frequencies due to complex logic and longer signal wiring lengths.
Innovation Solution
A multiport cache memory system where the address and data arrays are divided into banks identifiable by an index part lower-order bit, allowing simultaneous reading of target data from the same or different banks without contention by prioritizing access addresses and distributing cache block data to reading ports accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional bank structure is used to enable simultaneous reading operations, then multiport access capability is improved, but bank contention probability increases
Solution Approach 1:
The cache memory is divided into multiple banks (Bank 0, Bank 1, Bank 2, Bank 3) that can be independently accessed. Each bank is identified by lower-order bits of the index part of access addresses, allowing simultaneous reading operations to be distributed across different banks, thereby reducing bank contention probability while maintaining multiport access capability
2Reliability
If the number of banks is increased to reduce bank contention probability, then simultaneous access capability is improved, but cache memory area increases
Solution Approach 1:
The patent introduces a new dimension of bank identification using lower-order bits of the index part, rather than simply increasing the number of banks in a traditional manner. This allows efficient utilization of existing cache memory structure to reduce contention without proportionally increasing area
3Productivity
If cache memory area is increased to reduce bank contention, then simultaneous reading capability is improved, but signal wiring length increases
Solution Approach 1:
By segmenting the cache into banks identified by lower-order index bits, the patent enables compact bank organization that reduces signal wiring length compared to a monolithic structure, while maintaining simultaneous reading capability across multiple banks
4Reliability
If signal wiring length is increased to accommodate more banks, then bank contention is reduced, but operating frequency decreases
Solution Approach 1:
The patent uses lower-order bits of the index part for bank identification, which enables a compact bank layout that minimizes signal wiring length. This maintains high operating frequency while reducing bank contention through efficient bank organization rather than simply increasing wiring length
5Productivity
If LSI size is increased to reduce bank contention, then simultaneous access capability is improved, but power consumption increases
Solution Approach 1:
The cache memory is segmented into banks that can be independently accessed and controlled. This segmentation allows the system to activate only the necessary banks for each access operation, reducing power consumption compared to a monolithic structure where all components must be powered regardless of usage
Data Source
AI summary
A multiport cache memory is provided which enables reduction of a probability of bank contention which will occur when a plurality of read operations are executed simultaneously, and an access control system of the multiport cache memory.