Multi-port Circuit Architecture for Accurate Clock Power Reporting
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Solution Overview
Problem
Conventional processor designs face challenges in accurately reporting dynamic power consumption of sub-blocks in multi-port memories, as the number of conditions required for accurate power reporting becomes impractical, often leading to pessimistic or optimistic estimates.
Innovation Solution
Implementing a multi-port circuit architecture with multiple clock pins to model and report different powers for each port, allowing for more accurate tracking and simulation of clock power consumption, which fits within existing EDA tool infrastructure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock pin is used for multi-port memories, then device complexity is reduced, but measurement precision of power consumption deteriorates
Solution Approach 1:
The patent divides the single clock pin into multiple separate clock pins (CLKA, CLKB, CLKC, CLKD) corresponding to each port of the multi-port memory. This segmentation allows independent power reporting for each port while maintaining manageable device complexity through systematic organization.
2Measurement precision
If multiple clock pins are used for each port, then measurement precision of power consumption is improved, but device complexity increases
Solution Approach 1:
Each clock pin is designed with multi-functionality, serving both as a functional clock signal for its associated port and as a separate power reporting channel. This universal design allows the clock infrastructure to simultaneously drive memory operations and enable accurate power measurement without requiring separate dedicated pins.
3Productivity
If conventional single-port memory architecture is used, then routing congestion is reduced, but productivity of CPU design is worsened
Solution Approach 1:
The patent transitions from conventional single-port to multi-port architecture, adding the dimension of parallel port access. This enables simultaneous read/write operations across multiple ports, improving CPU design productivity and memory throughput while managing routing congestion through optimized interconnect design.
Data Source
AI summary
Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.