Multi-Port MAC Flexible Datapaths for Low-Latency Links
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Solution Overview
Problem
High-speed communication networks face latency issues due to the mismatch between data bus width and link speeds, leading to undesirable delays in packet processing, particularly in multi-port MACs with fixed datapaths.
Innovation Solution
Implementing a flexible datapath scheme in multi-port MACs using shared circuit blocks and a Time-Division Multiplexing (TDM) scheme to adjust datapath widths based on link speeds, allowing for lowest possible latency and reduced latency across varying link bandwidths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a wider data bus is used to support high-speed links, then throughput capability is improved, but latency increases due to longer data collection time
Solution Approach 1:
The patent implements dynamic datapath width adjustment where the MAC pipeline can configure different datapath widths (e.g., 32-bit, 64-bit, 128-bit) based on the link speed. At high speeds like 400G, a wider datapath is used for maximum throughput, while at lower speeds like 1G or 10G, a narrower datapath reduces the data collection time and associated latency. This dynamic reconfiguration resolves the contradiction by making the datapath width adaptive rather than fixed.
Solution Approach 2:
The patent changes the parameter of datapath width based on link speed requirements. The system can switch between different datapath configurations (e.g., from 64-bit at 400G to 32-bit at 10G) to optimize the balance between throughput and latency for each operating condition, directly addressing the contradiction between these two performance metrics.
2Device complexity
If a fixed datapath width is used in multi-port MACs, then device simplicity is maintained, but adaptability to different link speeds deteriorates
Solution Approach 1:
The patent creates a universal MAC pipeline that can handle multiple link speeds (1G, 10G, 25G, 400G) through a single configurable datapath structure. Instead of requiring separate fixed datapaths for each speed, the system uses one adaptable datapath that can be reconfigured, making the device versatile across different operating conditions while avoiding the need for multiple specialized hardware paths.
Solution Approach 2:
The datapath width is made dynamic and configurable based on the detected link speed. The MAC pipeline includes control logic that automatically adjusts the datapath width to match the operating speed, enabling a single device to adapt to various link speeds without requiring multiple fixed datapath designs, thus improving versatility while maintaining reasonable device complexity.
3Adaptability or versatility
If separate dedicated circuit blocks are provided for each datapath width, then support for multiple link speeds is improved, but real estate and power consumption increase
Solution Approach 1:
The patent merges multiple datapath width implementations into a single shared datapath structure that can be reconfigured. Instead of having separate dedicated circuit blocks for 32-bit, 64-bit, and 128-bit datapaths, the system uses one unified datapath that can be dynamically reconfigured to match the required width, thereby reducing the total hardware footprint and power consumption while maintaining support for multiple link speeds.
Solution Approach 2:
A universal datapath structure is designed that can serve multiple link speed requirements through reconfiguration. This single multi-functional datapath replaces what would otherwise require multiple separate dedicated datapaths, reducing the overall resource consumption and power usage while providing comprehensive support for various operating speeds.
Data Source
AI summary
Multi-port Media Control Channel (MAC) with flexible data-path width. A multi-port receive (RX) MAC block includes multiple RX ports and a plurality of RX circuit blocks comprising an RX MAC pipeline for performing MAC Layer operations on RX data received at the RX ports. The RX circuit blocks are connected with variable-width datapath segments, and the RX MAC block is configured to implement a multi-port arbitration scheme such as a TDM (Time-Division Multiplexed) scheme under which RX data received at a given RX port are forwarded over the variable-width datapath segments using datapath widths associated with that RX port. A multi-port transmit (TX) MAC block implementing a TX MAC pipeline comprising TX circuit blocks connected with variable-width datapath segments is also provided. The RX and TX MAC blocks include CRC modules configured to calculate CRC values on input data received over datapaths having different widths.