Multi-port Memory Bank Conflict Resolution
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Solution Overview
Problem
Conventional memory devices have limited write memory capacity, which is insufficient for high-speed network applications, and existing methods to increase write capacity are inefficient, requiring significant increases in area and power consumption, and are not easily scalable.
Innovation Solution
A multi-port memory device with a plurality of memory banks and an additional memory bank, where data blocks are written in a single clock cycle based on their addresses, allowing concurrent write operations to different or the same primary memory banks, and utilizing an additional memory bank to resolve conflicts, enabling efficient and scalable high-speed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory devices are used with single port architecture, then device complexity is low, but write capacity is limited and insufficient for high-speed network applications
Solution Approach 1:
The memory device is divided into multiple memory banks (first plurality, second plurality, and additional memory banks), each capable of independent write operations. This segmentation allows parallel write operations to different banks, increasing write capacity without proportionally increasing overall device complexity.
Solution Approach 2:
The additional memory banks serve multiple functions: they can be used for write operations when primary banks are occupied, provide backup storage, and enable concurrent write operations. This multi-functionality increases write capacity while minimizing the need for dedicated structures for each function.
2Quantity of substance
If conventional methods are used to increase write capacity, then write capacity increases, but area occupied and power consumption increase significantly
Solution Approach 1:
Multiple memory banks are merged into a single unified memory device with shared control logic and interconnect structures. This consolidation allows the device to achieve high write capacity through parallel banks while sharing common infrastructure, thereby reducing the area overhead compared to having separate memory devices.
Solution Approach 2:
The memory device utilizes multiple dimensions of parallelism by organizing memory banks in groups and enabling concurrent write operations across different bank groups. This dimensional approach to parallelism increases write capacity without linearly increasing area, as the parallelism is achieved through temporal and organizational dimensions rather than simply adding more physical memory cells.
3Quantity of substance
If conventional memory devices are used, then area occupied is minimized, but write capacity is limited and not easily scalable for higher capacities
Solution Approach 1:
The memory device is organized into modular bank groups (first plurality, second plurality, and additional memory banks) that can be independently configured and scaled. This segmentation allows the device to be easily scaled for higher write capacities by adding or configuring different numbers of bank groups, providing adaptability to various application requirements.
Solution Approach 2:
The memory device employs dynamic bank selection and configuration, where the controller can dynamically allocate and activate different memory banks based on write operation requirements. This dynamic approach enables the device to adapt to varying write capacity needs and be scaled for different applications without requiring a complete redesign.
4Productivity
If single port memory devices are used, then device complexity is low, but productivity is limited due to inability to support multiple concurrent write operations
Solution Approach 1:
The memory device is divided into multiple independently addressable memory banks that can perform write operations simultaneously. This segmentation enables multiple concurrent write operations to different banks, significantly increasing write throughput while keeping each individual bank relatively simple in structure.
Solution Approach 2:
The additional memory banks provide multi-functional capability, serving as primary write targets, backup storage, and concurrent operation targets. This universality allows the device to handle various write operation scenarios with a single unified architecture, increasing productivity without requiring multiple specialized memory structures.
Data Source
AI summary
It is determined whether more than one half of a plurality of data blocks are addressed to a same primary memory bank in a plurality of memory banks. If not more than one half of the data blocks in the plurality of data blocks are addressed to the same primary memory bank, the plurality of data blocks are written to appropriate ones of the primary memory banks in a single clock cycle. If more than one half of the data blocks are addressed to the same primary memory bank, (i) a subset of the data blocks addressed to the same primary memory bank are written to the same primary memory bank, and (ii) one or more remaining data blocks of the data blocks addressed to the same primary memory bank are written to an additional memory bank.