Multi-port Memory Bank Control with PLL Timing
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Solution Overview
Problem
Conventional single-port memory devices face difficulties in implementing multimedia functions due to their limited ability to allocate memory efficiently, leading to decreased utilization density, as they require each DRAM device to operate independently and manage multiple functions simultaneously.
Innovation Solution
A multi-port memory device with a bank control logic unit that includes a phase locked loop (PLL) for generating an internal clock signal, delay units for creating delayed clock signals, and a serializer to fit parallel data into corresponding data frames, along with a command decoder to generate command signals, allowing for simultaneous command generation across all bank controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single-port memory device is used to implement multimedia functions, then each DRAM device must operate independently, but this decreases the utilization density of memory resources
Solution Approach 1:
The memory device is divided into multiple independent banks (BANK0-BANK7) that can operate simultaneously. Each bank has its own control logic unit, allowing parallel access to different memory regions. This segmentation enables multiple multimedia functions to be implemented concurrently across different banks, improving both adaptability and memory utilization density without requiring independent DRAM devices.
2Productivity
If multiple bank controllers share the same ports, then resource utilization improves, but command signal skew between banks increases
Solution Approach 1:
A PLL unit generates a reference clock signal that is distributed to all bank controllers before command execution. Delay units are预先 configured to provide predetermined delay times to each bank controller, ensuring that command signals are synchronized across all banks before being applied. This preliminary timing adjustment prevents command skew and maintains timing accuracy while allowing multiple banks to share ports efficiently.
3Speed
If parallel data is applied to multiple bank controllers simultaneously, then operation speed increases, but timing skew between banks occurs
Solution Approach 1:
The system applies parallel data to all bank controllers simultaneously at a predetermined time point before actual command execution. Delay units are configured to provide predetermined delay times to each bank controller, ensuring that despite simultaneous data application, the commands are synchronized and applied at the correct timing for each bank, preventing timing skew while maintaining high operation speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient simultaneous command generation and data application across all bank controllers, minimizing skew and ensuring proper allocation of memory resources, thereby enhancing the memory device's ability to handle multiple operations concurrently.
Implementation Method 1
a phase locked loop (PLL) unit for generating an internal clock signal
Implementation Method 2
delay units for creating delayed clock signals
Data Source
AI summary
A multi-port memory device including a plurality of ports, a plurality of banks and a plurality of bank controllers, wherein all of the bank controllers share all of the ports, the device includes a phase locked loop (PLL) unit for generating an internal clock signal; a delay unit, provided in each bank controller, for generating first and second delayed clock signals by delaying the internal clock signal; a serializer, provided in each bank controller, for receiving a plurality of parallel data from all of the ports and fitting the parallel data for a corresponding data frame in response to the first delayed clock signal; and a command decoder, provided in each bank controller, for decoding output data of the serializer to generate command signals in response to the second delayed clock signal.