Multiport Memory Bit Line Vertical Stacking
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Solution Overview
Problem
Multiport semiconductor memory devices face performance degradation due to significant coupling capacitance between bit lines, which interferes with memory operations, especially during concurrent Read and Write operations, as existing twisted bit line techniques provide imperfect compensation.
Innovation Solution
The implementation of fully isolated bit line pairs with vertically stacked true and complementary bit lines, along with shared M2 and M3 power lines and orthogonal M4 and M1 power grids, ensures equivalent parasitic capacitance and prevents harmful coupling, enhancing memory cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If twisted bit line techniques are applied to single port memories, then some coupling compensation is achieved, but coupling capacitance issues persist during concurrent Read and Write operations in multiport memories
Solution Approach 1:
The bit line structure is segmented into true bit lines and complementary bit lines that are vertically stacked and isolated from each other. This segmentation separates the bit line pairs into distinct vertical layers, preventing lateral coupling between adjacent bit lines while maintaining the necessary signal differential structure for memory operations.
Solution Approach 2:
The patent transitions from a planar bit line arrangement to a vertical stacked configuration. By moving the complementary bit line to a different vertical layer (another dimension), the design eliminates lateral coupling capacitance while preserving the differential signal structure. This dimensional change allows bit lines to be isolated in the vertical direction while maintaining horizontal integration.
2Device complexity
If conventional bit line arrangements are used in multiport memories, then device complexity is reduced, but coupling capacitance causes performance degradation and malfunction
Solution Approach 1:
The patent merges the true bit line and complementary bit line into a single vertical stack structure. This combining approach reduces the overall lateral footprint and simplifies the routing layout while maintaining the differential signal structure. The merged vertical configuration reduces the number of lateral interconnections needed compared to separate planar arrangements.
Solution Approach 2:
By stacking bit lines vertically rather than arranging them laterally, the patent reduces planar complexity while improving performance. The vertical arrangement in the third dimension allows for simpler lateral routing and reduces coupling capacitance, effectively trading increased vertical structure complexity for reduced lateral complexity and improved electrical performance.
3Area of stationary object
If bit lines are placed close together to increase density, then area is reduced, but coupling capacitance between adjacent bit lines increases
Solution Approach 1:
The patent resolves the area-coupling contradiction by moving the complementary bit line to a vertical stack in the third dimension. This allows true bit lines to be placed close together laterally for high density while the vertical separation eliminates coupling capacitance. The area efficiency is maintained through compact lateral footprint while the vertical stacking removes the harmful coupling effect.
Solution Approach 2:
The vertical segmentation of bit lines into separate layers isolates adjacent true bit lines from each other electrically, even when placed close together laterally. This segmentation allows maximum lateral density while maintaining electrical isolation through the vertical insulating layers between stacked bit line pairs.
Data Source
AI summary
A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.