Multiport Memory Cell Shared Word Line Read Write Assist Transistor
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Solution Overview
Problem
Conventional multiport SRAM memory cell designs are port intensive, leading to increased area usage, power consumption, and the need for multiple wires and transistors, which complicates memory cell density and functionality.
Innovation Solution
A multiport memory cell with a shared word line structure and a read/write assist transistor that is activated during read operations and deactivated during write operations to optimize area usage and improve writeability, reducing the number of required wires and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate read and write ports are used (8T cell), then writeability and low Vdd functionality are improved, but area usage increases due to large number of wire pitches and active transistors
Solution Approach 1:
The patent merges read and write ports into a shared port structure, eliminating separate read and write transistors and wire pitches. This consolidation reduces area usage while maintaining writeability through the shared port's ability to perform both read and write operations.
Solution Approach 2:
The shared port is designed to serve dual functions as both read and write port, allowing the same hardware structure to perform multiple operations. This multi-functionality eliminates the need for dedicated read and write ports, thereby reducing area usage.
2Adaptability or versatility
If multiple separate wires and transistors are used for port intensive design, then memory cell functionality is improved, but device complexity and area usage increase
Solution Approach 1:
Multiple port functions are merged into a shared port structure, reducing the total number of wires and transistors required. The shared port handles both read and write operations, eliminating redundant hardware components.
Solution Approach 2:
The shared port is designed with universal functionality to handle both read and write operations, as well as support multiple bit lines. This multi-functionality reduces device complexity while maintaining comprehensive memory cell functionality.
3Productivity
If port intensive structure is used, then memory access capability is improved, but power consumption increases
Solution Approach 1:
The shared port structure merges read and write operations into a single hardware pathway, reducing the number of active transistors and wires that consume power. This consolidation maintains memory access capability while reducing overall power consumption.
Data Source
AI summary
A mutltiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and second bit lines coupled to the first memory access component, first and second bit lines coupled to the second memory access component, first and second write lines coupled to the first memory access component and first and second write lines coupled to the second memory access component. The multiport memory cell also includes a read/write assist transistor, coupled to load transistors of the data storing component, that during read operations is activated for the duration of the read operation and during write operations is activated to impress the desired voltage level before or after one or more memory access components activated as a part of the write operation are deactivated.