Multiport Memory Collision Control via Override Circuitry
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Solution Overview
Problem
Multiport memories face issues with collisions between concurrent data accesses, particularly when write and read operations occur simultaneously to the same bit cells, leading to unpredictable results and increased error likelihood due to fabrication process variations and reduced operation voltages.
Innovation Solution
The implementation of control circuitry and override circuitry that generates an override signal to actively drive bit values onto bit lines of other access ports during detected collisions, ensuring successful bit value flipping and reducing errors by overcoming the additional capacitance and downstream load challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional design approaches increase write drive strength and write pulse duration to overcome write/read collision, then write reliability is improved, but operation speed decreases and fabrication process variations become more significant
Solution Approach 1:
The patent introduces an intermediary mechanism (override circuitry with override signals) that mediates between write and read operations. When a write/read collision is detected, the override circuitry actively drives the write bit value onto the read port's bit lines, ensuring the write operation succeeds without requiring increased write pulse duration or drive strength, thereby maintaining high operation speed while improving write reliability
2Quantity of substance
If fabrication process size is reduced to increase integration density, then manufacturing capacity is improved, but device-to-device variation and corner case differences increase
Solution Approach 1:
The patent applies beforehand cushioning by proactively detecting potential write/read collisions through control circuitry that monitors port activity signals. When a collision is anticipated, override signals are generated in advance to actively drive the write value onto conflicting bit lines, cushioning against the increased variability and uncertainty inherent in smaller fabrication processes before the collision can cause an error
3Use of energy by moving object
If operation voltage is reduced to decrease power consumption, then energy efficiency is improved, but write/read collision errors become more likely
Solution Approach 1:
The patent implements feedback by using control circuitry that continuously monitors the activity signals from multiple ports. When a write operation is detected on one port and a read operation on another port accessing the same row, the control circuitry generates override signals that feed back to the write circuitry, enabling it to actively drive the write value onto the read port's bit lines and ensure successful write completion even at reduced operation voltages
4Productivity
If multiport memory is used to increase access capability and service multiple functional units, then productivity is improved, but collision conflicts between concurrent accesses increase
Solution Approach 1:
The patent applies dynamics by making the bit line driving capability dynamic rather than static. The override circuitry selectively activates additional driving strength on bit lines only when a write/read collision is detected through the control circuitry. This dynamic adjustment allows the memory to maintain high productivity with multiple concurrent access ports while ensuring data integrity by providing extra drive strength precisely when needed to overcome collision effects
Data Source
AI summary
A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access ports to a common row of bit cells. When such signals are detected, an override signal is generated and supplied to override circuitry 34, 36, 38, 40, 42, 44. The override circuitry is responsive to the override signal to drive one or more bit values being written to respective bit cells via their associated bit lines onto associated bit lines of other of a plurality of data access supports that are concurrently enabled for access to their bit cells. Thus, write data is also written onto the bit lines associated with a port performing a concurrent read operation.