Multiport Memory Dynamic Port Mapping for Collision Resolution
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Solution Overview
Problem
Multiport memories face issues with data access collisions, particularly write failures, due to asynchronous clock alignments between processors, leading to increased parasitic capacitance and access disturb noise, which can result in performance degradation and higher power consumption.
Innovation Solution
The implementation of dynamic port mapping, where colliding data access requests are routed to the same access control line and data lines as the conflicting request, allowing access control circuitry to reassign ports and lines efficiently, thereby avoiding the need to connect multiple bit lines to a storage cell, thus reducing capacitance and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple sets of bit lines are connected to storage cells to enable concurrent access from multiple ports, then data access speed is improved, but parasitic capacitance increases causing write failures
Solution Approach 1:
The patent implements dynamic port mapping where the association between memory ports and bit line sets is not fixed but can be changed during operation. When a collision is detected, the system dynamically reassigns ports to different bit line sets, allowing flexible adaptation to access patterns while maintaining the ability to serve multiple ports concurrently without permanently connecting all bit lines to all cells
Solution Approach 2:
The patent introduces access control circuitry as an intermediary layer between memory ports and storage cells. This intermediary detects collisions and manages bit line assignments, acting as a mediator that prevents direct conflict between simultaneous writes to the same row by controlling which port can access which bit lines at any given time
2Adaptability or versatility
If both word lines to the same row are turned on simultaneously to allow access from different ports, then access versatility is improved, but write failures occur due to conflicting bit line signals
Solution Approach 1:
The access control circuitry implements feedback by monitoring access requests from multiple ports and detecting when collisions occur. Based on this feedback, the system dynamically adjusts bit line assignments to prevent conflicting write operations, ensuring that write reliability is maintained while still allowing versatile concurrent access when no conflicts exist
3Reliability
If dynamic port mapping is implemented to resolve collisions, then write reliability is improved, but device complexity increases due to additional access control circuitry
Solution Approach 1:
The access control functionality is segmented into modular components: collision detection logic, port mapping management, and bit line assignment control. This segmentation allows the complex function of collision resolution to be broken down into manageable, independent modules that can be implemented efficiently in hardware without overwhelming complexity
4Productivity
If multiple bit lines are connected to storage cells for multiport access, then data access concurrency is improved, but noise increases causing access disturb
Solution Approach 1:
The patent extracts the conflict resolution function from the physical connection structure itself and places it in the access control logic. Instead of preventing all potential conflicts by limiting physical connections, the system allows multiple bit lines to be available but actively selects and activates only the appropriate subset for each access operation, thereby reducing noise from inactive bit lines while maintaining high concurrency capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively mitigates data access collisions without increasing capacitance or noise, enabling faster access times, lower power consumption, and smaller device sizes, while maintaining efficient data access without write failures.
Implementation Method 1
each storage cell comprising data storage circuitry and a plurality of access control devices for isolating said storage circuitry from or connecting said storage circuitry to a data line, said memory comprising a plurality of sets of access control lines and corresponding data lines
Implementation Method 2
said access control circuitry comprising collision detection circuitry configured to detect a colliding data access request received at a second data access port that requests access to a row of storage cells currently being accessed by a data access request received at a first data access port
Data Source
AI summary
A multiport memory having an array of storage cells for storing data; a plurality of data access ports; and access control circuitry to assign each data access port to one of the sets of access control lines and corresponding data lines. The control circuitry has collision detection circuitry to detect a colliding data access request received at a second data access port that requests access to a row of storage cells currently being accessed by a data access request received at a first data access port. The control circuitry is responsive to the detected collision to assign the set of access control lines and corresponding data lines currently assigned to the first data access port to the second data access port and to subsequently assign the first data access port to the set of access control lines and corresponding data lines previously assigned to the second access port.