Multi-port Memory Buffering Host and NAND Flash Speed Mismatch
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Solution Overview
Problem
NAND type flash memory devices operate at a lower speed than DRAM, which can reduce mobile system performance and increase CPU package size due to the need for separate interfaces, making them less suitable for applications requiring high storage capacity like image data in mobile phones.
Innovation Solution
A multi-port memory device with a volatile main memory core and a sub memory core, along with interface circuits, allows for data transfer between a host system and non-volatile memory, enabling the DRAM to act as a buffer and control NAND flash memory operations, effectively increasing the speed of data access and reducing system size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND type flash memory is used for high capacity storage, then storage capacity is improved and cost is reduced, but operating speed deteriorates
Solution Approach 1:
The patent introduces a DRAM buffer as an intermediary component between the host CPU and NAND flash memory. The DRAM buffer temporarily stores data during transfer operations, allowing the CPU to write data to the buffer at high speed while the slower flash memory performs background transfers from the buffer. This mediator resolves the speed mismatch between fast CPU operations and slow flash memory operations.
2Productivity
If separate interfaces are provided for DRAM and NAND flash memory, then data transfer capability is improved, but CPU package size increases
Solution Approach 1:
The patent merges the DRAM buffer and NAND flash memory interface operations into a unified control architecture. The CPU package includes both the DRAM controller and flash memory controller integrated together, allowing shared control logic and coordinated operation. This integration enables the system to maintain separate data transfer paths while reducing the overall package size through shared components and coordinated control.
Data Source
AI summary
A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core can be configured to store data received thereat and read requested stored data therefrom. A main interface circuit can be coupled to the first port and can be configured to provide data to/from the volatile main memory core and the first port in a master mode and can be configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port can be configured for data transfer to/from an external non-volatile memory device and the device and a sub interface circuit can be coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.