Multiport Memory Latch Circuit Timing Relaxation
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Solution Overview
Problem
The existing pseudo 2-port SRAM circuits face timing constraints that hinder the improvement of operating frequency due to strict setup and hold times for selection control signals relative to word line control signals, leading to potential malfunctions and reduced performance.
Innovation Solution
The proposed multiport memory design includes an address control circuit with latch circuits, a selection circuit, and a word line drive circuit, where address signals from two ports are latched and decoded to drive word lines, relaxing timing constraints by separating the selection control signal processing from the word line drive signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If address signals are directly supplied to decoders without latching, then operating frequency can be improved, but setup and hold time constraints become too strict causing potential malfunctions
Solution Approach 1:
The patent applies preliminary action by latching address signals before they are supplied to decoders. The latch circuits capture address signals at appropriate timing, preparing them in advance for decoder processing. This preliminary latching action relaxes setup and hold time constraints while maintaining reliable operation, as the signals are stabilized before decoding occurs.
2Reliability
If latch circuits are inserted between address input and decoder, then timing constraints are relaxed, but device complexity increases
Solution Approach 1:
The latch circuits in the patent serve multiple functions: they act as address signal buffers, timing synchronization elements, and setup/hold time management components. By making the latch circuits multi-functional, the patent reduces overall device complexity while still achieving reliable timing constraint compliance. The same latch structure performs several critical functions that would otherwise require separate circuit elements.
3Reliability
If address signals are latched before decoder, then word line malfunction is reduced, but access time increases
Solution Approach 1:
The patent maintains continuity of useful action by ensuring that the latched address signals are immediately supplied to the decoders without unnecessary delays. The latch circuits are designed to hold signals ready for decoding, creating a continuous flow from address input through latching to decoding and word line activation. This continuous action minimizes access time while maintaining reliability.
Data Source
AI summary
A semiconductor device includes a latch circuit receiving a first signal, generated in synchronization with a clock signal, from a pulse generation circuit, and generating a second signal; a first delay circuit receiving the second signal from the latch circuit, and generating a third signal by delaying the second signal; a second delay circuit receiving the third signal from the first delay circuit, and generating a fourth signal by delaying the third signal; and a logic circuit receiving the second and fourth signals from the latch and second delay circuits, respectively, and generating a word line control signal based on one of the second signal and the fourth signal. The latch circuit generates the second signal of a first level based on the first signal, and generates the second signal of a second level, which is different from the first level, based on the third signal.