Multi-port Memory Array Output Network Conflict Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dual-read-port memory arrays with single-read-port memory elements face conflicts when multiple read requests access the same memory subblock, leading to performance issues due to resource sharing, which existing technologies fail to resolve efficiently.
Innovation Solution
A multi-read-port memory array design with an output network that redirects information from one read port to another if their addresses are the same, using a comparator and multiplexers to resolve conflicts and improve performance by allowing all read requests to be satisfied from the same memory subblock access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If dual-read-port memory arrays are implemented with single-read-port memory elements, then area and power efficiency are improved, but conflicts occur when multiple read requests access the same memory subblock
Solution Approach 1:
An output network is introduced as an intermediary component between the memory subblocks and read ports. This network includes multiplexers that detect address equivalency and redirect read operations, serving as a mediator that prevents conflicts without requiring complex changes to the memory cells themselves.
Solution Approach 2:
The memory array is divided into multiple memory subblocks, each with its own output network. This segmentation allows independent handling of read requests at the subblock level, enabling conflict resolution to occur locally rather than requiring global arbitration across the entire memory array.
2Adaptability or versatility
If arbitration processes are implemented to resolve conflicts, then resource sharing is improved, but timing performance is degraded
Solution Approach 1:
Address equivalency detection is performed preliminarily, in parallel with the memory read operation itself. The output network compares addresses and determines potential conflicts before the read operation completes, allowing immediate redirection without waiting for traditional arbitration to occur after the conflict is detected.
Solution Approach 2:
The output network maintains continuous operation by processing address comparisons and redirection decisions in parallel with memory read operations. This eliminates idle arbitration periods and ensures that the read pipeline remains continuously productive, with no loss of timing performance.
3Productivity
If dual-read-port memory cells are used, then data throughput is improved, but area and cost increase
Solution Approach 1:
Multiple read port functionalities are merged into a single read port per memory subblock. The output network combines the address comparison, conflict detection, and data routing functions that would otherwise require separate dual-read-port cell structures, achieving dual-port functionality with single-port cells.
Solution Approach 2:
The output network is designed as a universal interface that handles multiple read requests from different ports through a single memory subblock. It provides multi-functional capability by detecting address patterns, redirecting reads, and managing resource sharing, replacing the need for specialized dual-read-port memory cells.
Data Source
AI summary
A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a condition that an equivalence signal indicates that read addresses for the first read port and the second read port are the same. The latching and multiplexing operation may be integrated. The memory cells may be 6-transistor synchronous random access memory (SRAM) cells, 8-transistor SRAM cells, or any type of memory cells.