Multiport Memory Architecture with Port Buffers and Common Buses
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Solution Overview
Problem
Conventional multiport memory architectures face limitations in operational speed due to the disparity between network speeds and memory array speeds, leading to increased latency and reduced throughput, especially as network demands increase.
Innovation Solution
The proposed solution involves a multiport memory architecture where port buffers are tightly coupled to the main memory, utilizing common buses for data transmission and reception, eliminating the need for FIFO buffers, and employing point-to-point communications to reduce RC components and parasitics in memory busses, thereby enhancing data transmission rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FIFO buffers are used to bridge network speeds and memory array speeds, then data transfer compatibility is improved, but device complexity and latency increase
Solution Approach 1:
The patent removes the FIFO buffer component from the traditional multiport memory architecture. By eliminating the FIFO buffer that sits between ports and memory array, the design reduces complexity while maintaining the ability to handle different data rates through the port buffer's inherent buffering capability and common bus structure.
Solution Approach 2:
The patent merges the buffering function into the port buffer itself rather than having a separate FIFO buffer. The port buffer handles both data conversion and buffering functions, integrating multiple functions into a single component and simplifying the overall architecture.
2Reliability
If dedicated write busses are provided for each FIFO buffer, then data transmission reliability is improved, but bus width and die area increase
Solution Approach 1:
The patent implements a universal common bus structure that serves all port buffers for both read and write operations. This single common bus replaces what would traditionally require multiple dedicated busses, reducing the total bus width and die area while maintaining reliable data transmission through the shared access mechanism.
3Productivity
If memory bus width is increased to improve throughput, then data transmission rate is improved, but RC components and parasitics increase
Solution Approach 1:
The patent segments the data transmission path into point-to-point connections from ports to port buffers, then uses a common bus for memory access. This segmentation allows the critical path from ports to memory to be broken into smaller segments with controlled impedance, reducing cumulative RC effects and parasitics compared to a single wide bus.
Solution Approach 2:
The port buffer acts as an intermediary between the ports and the common bus. This intermediary structure allows data to be buffered and prepared at the port level before being placed on the common bus, reducing the impact of bus capacitance and resistance on the overall transmission speed.
4Productivity
If network ports operate at high speeds (1 GHz), then network throughput is improved, but memory access becomes the bottleneck
Solution Approach 1:
The patent implements preliminary buffering at the port level before data reaches the memory array. The port buffer temporarily stores incoming data at high speed, allowing the memory array to be accessed at its own optimized speed without being constrained by the faster network port speeds, thus eliminating the bottleneck.
Solution Approach 2:
The architecture allows different components to operate at different speeds dynamically. The port buffers can operate at network speeds (1 GHz) while the memory array operates at its optimized speed (100-200 MHz), with the common bus coordinating these different operating frequencies through controlled access timing and protocols.
Data Source
AI summary
A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.