Multi-port 1R1RW Memory Architecture for Read Bandwidth
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Solution Overview
Problem
Conventional memory designs face performance and efficiency issues due to access conflicts in multi-bank memory systems, which are exacerbated by increasing the number of read ports or memory banks, leading to power, performance, and area (PPA) penalties.
Innovation Solution
A novel multi-port 1R1RW memory architecture is introduced, featuring an additional sense amplifier at the write-port, allowing for 2-Reads or 1Read-1Write operations in one clock cycle without introducing memory access conflicts, thereby improving read bandwidth and reducing conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of read ports is increased to improve performance, then read bandwidth is improved, but access conflicts increase adversely impacting performance
Solution Approach 1:
The memory system is divided into multiple independent memory banks, each capable of handling read operations independently. This segmentation allows multiple reads to proceed simultaneously across different banks without conflicts, while each bank maintains its own read port structure to avoid internal conflicts.
Solution Approach 2:
The patent introduces a new dimensional approach by adding a write port with dedicated write bitlines and sense amplifiers that operate in a separate dimension from read operations. This allows read and write operations to occur simultaneously without interfering with each other, effectively adding a temporal dimension to the memory access model.
2Reliability
If the number of memory banks is increased to avoid access conflicts, then access conflict frequency is reduced, but layout efficiency deteriorates due to area inefficiency of smaller banks
Solution Approach 1:
Each memory bank is designed with multi-functional capability to handle both read and write operations through shared bitlines and sense amplifiers during appropriate cycles. The write port structure provides universal access capability across all banks, reducing the need for additional dedicated structures in each bank and improving layout efficiency.
Solution Approach 2:
The patent changes the operational parameters of memory banks by enabling them to dynamically switch between read-only mode and write-capable mode. This parameter change allows smaller banks to be more area-efficient while maintaining low conflict frequency through coordinated access control across the multi-port structure.
3Device complexity
If conventional single-port memory architecture is used, then device complexity is low, but performance is limited due to unintended conflicts in multi-bank memory access
Solution Approach 1:
The patent introduces write bitlines and dedicated write sense amplifiers as intermediary elements that mediate between the write port and memory banks. These intermediaries enable write operations to proceed independently without conflicting with read operations, thereby improving performance while maintaining manageable complexity through structured intermediate components.
Solution Approach 2:
The memory architecture employs dynamic operation modes where banks can be selectively activated for read or write operations based on current access patterns. This dynamic behavior allows the system to optimize performance for different workloads while maintaining a relatively simple base structure that only becomes more complex when dynamic features are activated.
Data Source
AI summary
Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.