Multi-port Memory Arrays Using Segmented Standard Cells
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Solution Overview
Problem
Current multi-port memory systems face challenges in achieving efficient memory density, performance, and power consumption due to the need for custom designs or inefficient synthesized solutions, which are costly and time-consuming.
Innovation Solution
The development of multi-port memory arrays constructed from standard circuit components, including bus keeper circuits and tri-state buffer circuits, to create efficient multi-port memory systems that can be easily integrated into integrated circuit designs using automated design tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional transistors are added to create multi-port memory cells, then concurrent memory access capability is improved, but memory density deteriorates
Solution Approach 1:
The patent segments the memory access function by separating read and write operations into distinct ports. Each port has dedicated transistors and circuitry, allowing independent concurrent operations. This segmentation enables multiple memory users to access the same cell simultaneously without interference, resolving the contradiction between access capability and density.
Solution Approach 2:
The patent merges multiple single-port memory cells into a single multi-port memory cell structure. By combining the functionality of multiple cells while sharing the same storage capacitance and organizing transistors in parallel configurations, the patent achieves concurrent access from multiple ports without proportionally increasing the total transistor count, thus maintaining memory density.
2Adaptability or versatility
If additional transistors are added to create multi-port memory cells, then concurrent memory access capability is improved, but power consumption deteriorates
Solution Approach 1:
The patent applies local quality by making certain transistors larger in size specifically for read operations, while keeping write transistors smaller. This differential sizing optimizes the power consumption for each operation type - larger read transistors provide lower impedance for faster readout when needed, while smaller write transistors reduce overall power consumption during write operations, thus managing power usage in concurrent multi-port access scenarios.
3Quantity of substance
If custom multi-port memory arrays are designed, then memory density and performance are improved, but design cost and time deteriorate
Solution Approach 1:
The patent uses standardized memory cell templates and pre-verified circuit modules that can be copied and instantiated multiple times. Instead of designing custom multi-port memory arrays from scratch, the invention reuses proven cell structures and configurations, significantly reducing design time and cost while maintaining optimal memory density and performance characteristics.
4Loss of time
If standard synthesis tools are used to create multi-port memory, then design time is reduced, but efficiency deteriorates
Solution Approach 1:
The patent modifies standard synthesis tool parameters and configurations to optimize the generated multi-port memory structures. By adjusting synthesis parameters such as transistor size ratios, port configurations, and cell layouts, the invention transforms the output of standard synthesis tools into efficient, high-density memory structures that would otherwise require custom design, thus maintaining short design times while improving memory density.
Data Source
AI summary
Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.