Multi-port Memory Device Serial Interface Mode Register
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Solution Overview
Problem
Conventional semiconductor memory devices with parallel I/O interfaces face limitations in supporting concurrent operations due to increased manufacturing costs and complexity, particularly in multi-media systems requiring independent data processing, necessitating a shift to serial I/O interfaces for efficient data transmission.
Innovation Solution
A multi-port semiconductor memory device with a serial input/output interface is designed, featuring multiple ports and banks that can switch between serial and parallel access modes through a mode register, allowing for efficient data access and testing operations by determining the access mode based on input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a parallel I/O interface is used to achieve high-speed data transmission, then data processing efficiency is improved, but the number of buses increases leading to increased manufacturing cost and device complexity
Solution Approach 1:
The patent replaces the mechanical/electrical parallel bus system with a serial communication system. Instead of using multiple physical buses for parallel data transmission, the invention uses a single serial bus that transmits data bit-by-bit sequentially, thereby reducing the number of physical connections while maintaining data transmission capability
Solution Approach 2:
The serial bus is designed to perform multiple functions: it can transmit data, addresses, and control signals all through the same single bus structure. This multi-functional design eliminates the need for separate dedicated buses for each type of signal, reducing overall system complexity
2Adaptability or versatility
If multiple memory devices are independently configured to support various multi-media functions, then functional versatility is improved, but the inability to perform concurrent operations reduces productivity
Solution Approach 1:
The patent merges multiple independent memory device functions into a single multi-port memory device. By integrating multiple ports within one device, it enables concurrent operations across different ports while maintaining the functional versatility needed for various multi-media applications
Solution Approach 2:
The memory device is segmented into multiple independent ports, each capable of handling operations independently. This segmentation allows different ports to perform concurrent operations simultaneously, improving overall productivity while maintaining functional versatility
3Device complexity
If a serial I/O interface is used to reduce the number of buses and manufacturing cost, then device complexity is reduced, but data transmission speed decreases compared to parallel interface
Solution Approach 1:
The serial communication system operates continuously without the need for complex synchronization and setup that parallel interfaces require. By maintaining constant data flow through the serial bus and eliminating idle periods associated with parallel bus management, the system achieves efficient data transmission despite the serial nature
Data Source
AI summary
A semiconductor memory device includes plural ports for transmitting an input data serial-interfaced with an external device into a global data bus, plural banks for parallel-interfacing with the plural ports through the global data bus, plural input signal transmission blocks, responsive to a mode register enable signal, for transmitting an input signal parallel-interfaced with the external device into the global data bus, and a mode register set for determining one of a data access mode and a test mode based on the input signal inputted through the global data bus.