Multiport Memory Status Notification for Data Transfer Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current multiport memory systems face challenges in achieving high-speed data communication between information processing devices due to delayed data transfer methods, which cannot keep pace with the faster speeds required by modern information processing systems.
Innovation Solution
A multiport memory system is designed with a configuration that allows immediate status updates from one port to another, utilizing registers like timing, status notification, shared area, and master registers to manage and prioritize requests, enabling efficient data communication by dynamically allocating memory areas and arbitrating requests to optimize data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data communication between ports uses traditional handshake method through Mail Box, then data transfer is reliable, but data communication speed is delayed and cannot cope with higher speeds
Solution Approach 1:
The patent applies preliminary action by pre-establishing direct data pathways between ports and pre-configuring status notification mechanisms. Instead of waiting for handshake completion, the system prepares data transfer routes in advance and notifies status changes immediately, eliminating the sequential delays inherent in traditional handshake methods.
Solution Approach 2:
The patent introduces status notification signals as intermediaries that directly convey data transfer status between ports without requiring full handshake sequences. These intermediary signals enable asynchronous communication where ports can independently track and respond to data status changes, significantly reducing communication latency.
2Adaptability or versatility
If memory areas are statically assigned to particular ports, then port operations are simple, but data communication flexibility and speed are reduced
Solution Approach 1:
The patent implements dynamic memory area allocation where memory regions can be flexibly assigned to different ports based on real-time communication needs. The memory control circuit dynamically adjusts which ports can access which memory areas, allowing optimal adaptation to varying data communication requirements without static constraints.
Solution Approach 2:
The patent employs feedback mechanisms where ports notify the memory control circuit of their data communication needs, and the circuit responds by appropriately allocating memory areas. This feedback loop enables adaptive memory management that balances flexibility with controlled complexity through systematic resource allocation.
Data Source
AI summary
In an information processing system, a plurality of information processing devices CHIP0 and CHIP1 are connected to multiport memory MPMEM0 that has a plurality of ports, and memory areas in multiport memory MPMEM0 can be altered to memory areas occupied by particular ports and memory areas shared by a plurality of ports. At such times, immediately after the occurrence of a request from a port, the status of this request may be supplied from other ports.