Multiport NVMe Controller Shared Logic Area Reduction
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Solution Overview
Problem
Prior implementations of NVMe controllers for multipath I/O operations require large gate counts and complexity, making them inefficient in terms of area and performance.
Innovation Solution
An optimized multiport NVMe controller design that shares common logic among controllers, including a DMA Engine, Firmware Request Queue, Firmware Completion Queue, and DMA Completion Queue, significantly reducing gate count and area while maintaining performance by using dedicated queues for each host and independent command arbitration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate discrete NVMe controllers are used for multipath I/O, then reliability and fault tolerance are improved, but device complexity and gate count increase significantly
Solution Approach 1:
The patent merges multiple NVMe controller instances into a single integrated controller device that supports multipath I/O. Multiple controller instances share common resources including DMA engines, firmware request queues, firmware completion queues, and DMA completion queues, while maintaining independent namespaces for different hosts. This consolidation reduces overall gate count and device complexity while preserving fault tolerance through namespace isolation and independent command processing paths.
Solution Approach 2:
The controller implements universal resources that serve multiple controller instances simultaneously. A single DMA engine can service multiple namespaces, firmware queues are shared across instances, and the controller maintains the ability to independently process commands for different hosts. This multi-functionality reduces resource duplication and lowers gate count while maintaining the reliability benefits of multipath I/O.
2Adaptability or versatility
If multiple discrete controllers are implemented for multipath I/O, then namespace sharing among hosts is enabled, but area and manufacturing cost increase
Solution Approach 1:
The patent combines multiple controller instances into a single physical device that supports namespace sharing among multiple hosts. The controller maintains independent namespace structures for each host while sharing common hardware resources such as DMA engines and firmware queues. This approach enables namespace sharing functionality without requiring separate physical controllers for each host, thereby reducing the total area occupied on the PCIe card.
Solution Approach 2:
The controller is segmented into independent functional units that can be independently configured for different namespaces. Each namespace can be independently managed and assigned to different hosts, while the underlying hardware resources are shared. This segmentation allows flexible namespace allocation across multiple hosts without requiring dedicated hardware for each namespace, reducing overall area requirements.
3Productivity
If independent queues are provided for each host, then command processing performance is improved, but device complexity increases
Solution Approach 1:
The patent merges the queue management functionality into shared firmware queues that are accessible by multiple controller instances. The firmware request queue and firmware completion queue are common resources that handle commands from multiple hosts through a unified management structure. This approach maintains independent command processing paths for performance while using shared queue infrastructure to reduce the complexity of managing separate queues for each host.
Data Source
AI summary
This provides an optimized multiport NVMe controller on a single die that significantly reduces area and gate count for multipath I/O requirements over prior implementations without compromising any performance requirements. The arrangement implements minimal logic per NVMe controller as per NVMe specification requirements and implements shared logic for all common functions. This results in the desired substantial savings in gate count and area. The optimized multiport NVMe controller is used in multipath I/O-based memory subsystem where multiple hosts access Namespaces through their own dedicated queues. Illustratively, the optimized multiport NVMe controller shares common logic among NVMe controllers, providing area efficient solution for multipath I/O implementations. Shared logic across all NVMe controllers are the DMA Engine (Hardware block which handles all NVMe commands based on PRP or SGL pointers), Firmware Request Queue (FWRQ). Firmware Completion Queue (FWCQ) and DMACQ (DMA Completion Queue).