Multiport SRAM Bit Line Control for Predictable Access
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Solution Overview
Problem
Multi-port memory devices face challenges in coordinating access to memory cells, leading to unpredictable access times due to the need for wait states and arbitration, which is undesirable in high-speed reading/writing operations.
Innovation Solution
The solution involves decoupling the bit line pair of one port from the storage nodes of the selected memory cell when both ports access the same bit cell, using row and column match detectors to manage access, ensuring that only one port's bit line pair is actively coupled to the data line pair, thereby avoiding capacitance issues and stabilizing bit cell access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple ports access the same memory cell simultaneously using separate bit line pairs, then memory access parallelism is improved, but capacitance increases and access time becomes unpredictable
Solution Approach 1:
The patent applies preliminary action by detecting address matches between ports before memory access occurs. The row match detector and column match detector identify potential conflicts in advance, allowing the system to preemptively select a single bit line pair for the access operation, thereby preventing capacitance issues and ensuring predictable access times before they can arise.
Solution Approach 2:
The patent introduces intermediary components (row match detector, column match detector, and selection logic) that mediate between multiple ports and the memory array. These intermediaries detect address matches and selectively couple only one port's bit line pair to the memory cell, acting as a buffer that prevents direct capacitance conflicts while maintaining access parallelism through intelligent routing.
2Adaptability or versatility
If multiple bit line pairs are coupled to the same memory cell, then access flexibility is improved, but capacitance increases and bit cell stability deteriorates
Solution Approach 1:
The system performs preliminary detection of address matches using row match detectors and column match detectors before coupling bit line pairs to memory cells. This preliminary action identifies when multiple ports are accessing the same cell, allowing the selection logic to preemptively couple only one bit line pair, thereby maintaining bit cell stability while preserving access flexibility through the detection and resolution mechanism.
Solution Approach 2:
The patent introduces intermediary detection and selection logic between multiple ports and the memory array. These intermediaries monitor address signals, detect matches, and selectively enable only one bit line pair coupling to each memory cell, acting as a protective buffer that maintains bit cell stability while allowing flexible multi-port access configurations.
3Reliability
If wait states and arbitration are used to coordinate multi-port access, then access coordination is improved, but access time increases and speed decreases
Solution Approach 1:
The patent applies preliminary action by detecting address matches between ports before memory access occurs. The row match detector and column match detector identify potential conflicts in advance, allowing the system to preemptively select a single bit line pair for the access operation, thereby preventing capacitance issues and ensuring predictable access times before they can arise.
Solution Approach 2:
The patent introduces intermediary components (row match detector, column match detector, and selection logic) that mediate between multiple ports and the memory array. These intermediaries detect address matches and selectively couple only one port's bit line pair to the memory cell, acting as a buffer that prevents direct capacitance conflicts while maintaining access parallelism through intelligent routing.
Data Source
AI summary
In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic. A second data line pair is coupled to the first bit line pair via second switching logic and to the second bit line pair via third switching logic. If a row address match but not a column address match exists between a first and second access address, the second switching logic selectively connects the second data line pair with the first bit line pair based on a first decoded signal generated from the column address of the second access address and the third switching logic decouples the second data line pair from the second bit line pair.