Multi-port Storage Bypassing Processor Interconnects
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Solution Overview
Problem
In multi-socket processing systems, accessing memory subsystems across different processor nodes introduces latency due to the need for processor interconnect usage, especially during high memory access operations in Non-Uniform Memory Access (NUMA) configurations.
Innovation Solution
A multi-port storage device system that uses memory and connection mappings to directly access local memory subsystems without relying on processor interconnects, allowing storage controllers to execute memory access commands efficiently by identifying the correct local memory and connection for each processor node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If storage controllers access memory subsystems through processor interconnects in NUMA configurations, then system compatibility and memory accessibility are maintained, but access latency increases and performance deteriorates
Solution Approach 1:
The system segments memory access paths by implementing separate direct access channels from storage controllers to memory subsystems, bypassing the processor interconnect. This is achieved through dedicated memory access interfaces and separate physical or logical pathways that allow storage controllers to directly reach local memory subsystems without traversing the processor interconnect, thereby reducing access latency and improving memory access speed.
Solution Approach 2:
The patent introduces an intermediary memory access interface that facilitates direct communication between storage controllers and memory subsystems. This intermediary layer enables storage controllers to access memory without requiring processor interconnect mediation, effectively creating a dedicated access path that eliminates the performance bottleneck while maintaining system compatibility and memory accessibility.
2Productivity
If processor interconnect is used for both processing communications and storage memory access, then system resource sharing is optimized, but processing bottlenecks occur during high memory access operations
Solution Approach 1:
The system divides the access path infrastructure into separate segments: one path for processor communications and another for storage memory access. This segmentation is implemented through dedicated memory access interfaces and separate physical or logical channels, allowing both processor communications and storage operations to proceed simultaneously without interfering with each other, thereby eliminating processing bottlenecks while maintaining resource sharing efficiency.
3Adaptability or versatility
If dual port SSD storage devices connect to different processor devices, then memory access capability across NUMA nodes is enabled, but access latency increases due to interconnect traversal
Solution Approach 1:
The system implements local quality by establishing direct access paths from each storage controller to the local memory subsystem of its connected processor. This local access optimization ensures that storage controllers can quickly access memory resources without traversing the processor interconnect, even in multi-socket NUMA configurations. The solution maintains adaptability across different processor devices while improving access speed through localized direct access paths.
Data Source
AI summary
A multi-port storage device multi-socket memory access system includes a plurality of processing subsystems interconnected by at least one processing subsystem interconnect, a respective local memory subsystem for each of the processing subsystems, and a storage system that provides a respective connection to each of the processing subsystems. The storage system receives a memory access command and uses it to determine a first local memory subsystem that includes a memory location that is identified in the memory access command. The storage system then uses a connection mapping to identify a first connection to a first processing subsystem for which the first local memory subsystem is provided. The storage system then accesses the first memory subsystem through the first connection, via the first processing system, and without utilizing the at least one processing subsystem interconnect, in order to execute the memory access command.