Multiported Memory Supercell with Dedicated Access Ports
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Solution Overview
Problem
In integrated circuits, existing memory hierarchies face inefficiencies in data access and transfer due to the lack of dedicated access ports for memory bank groups, leading to increased latency and power consumption.
Innovation Solution
The integration of a memory supercell with multiple bank groups, each having a dedicated access port and a switch unit that connects memory requesters to the appropriate bank group based on request signals, allowing for concurrent read and write operations and reducing data transfer distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a memory supercell uses a single shared interface for all memory banks, then device complexity is reduced, but data access latency increases and power consumption increases due to longer data transfer distances
Solution Approach 1:
The memory supercell is segmented into multiple bank groups (e.g., first bank group, second bank group), each with its own dedicated access port. This segmentation allows different bank groups to be accessed simultaneously through different ports, reducing data access latency by enabling parallel access operations.
Solution Approach 2:
A switch unit is introduced as an intermediary component between memory requesters and the bank groups. The switch unit dynamically connects requesters to the appropriate bank group based on access requests, enabling efficient routing of data transfers and reducing the effective data transfer distance while maintaining structural organization.
2Device complexity
If a memory supercell uses a single shared interface for all memory banks, then device complexity is reduced, but power consumption increases due to longer data transfer distances
Solution Approach 1:
The memory supercell is divided into multiple bank groups with dedicated access ports, reducing the physical distance data must travel between the interface and memory banks. This segmentation decreases power consumption by minimizing data transfer distances while maintaining a manageable structural complexity through systematic organization.
Solution Approach 2:
Each bank group is equipped with its own dedicated access port, creating local access points that reduce the average data transfer distance. This local quality improvement allows data to be accessed closer to its storage location, reducing power consumption without requiring a complete redesign of the entire memory interface structure.
3Productivity
If a memory supercell allows concurrent read and write operations across different bank groups, then productivity increases, but device complexity increases due to additional access ports and switching circuitry
Solution Approach 1:
The memory supercell is segmented into multiple independent bank groups, each with its own dedicated access port. This segmentation enables concurrent read and write operations to occur simultaneously in different bank groups, improving productivity while the modular structure keeps the increase in device complexity manageable and systematic.
Solution Approach 2:
A dynamic switch unit is implemented to manage connections between memory requesters and bank groups. The switch unit adaptively routes data flows based on operation type (read/write) and target bank group, enabling flexible concurrent operations. This dynamic control mechanism improves productivity while the switching logic, though adding complexity, provides systematic management of the multiple access ports.
Data Source
AI summary
An integrated circuit. The integrated circuit includes a plurality of memory requesters and a memory supercell. The memory supercell includes a plurality of memory banks each of which forms a respective range of separately addressable storage locations, wherein the memory supercell is organized into a plurality of bank groups. Each of the plurality of bank groups includes a subset of the plurality of memory banks and a corresponding dedicated access port. The integrated circuit further includes a switch coupled between the plurality of memory requesters and the memory supercell. The switch is configured, responsive to a memory request by a given one of the plurality of memory requesters, to connect a data path between the given memory requester and the dedicated access port of a particular one of the bank groups addressed by the memory request.