Multi-Ported Storage Array Layout With Clock-Gated Register Writes
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Solution Overview
Problem
Current memory technologies, such as standard SRAMs and vendor-provided SRAM compilers, struggle to efficiently generate multi-ported storage arrays, leading to poor performance, high complexity, and inefficient use of silicon area due to their reliance on behavioral descriptions and random logic synthesis, which fail to exploit the structural properties of these arrays.
Innovation Solution
The method involves generating a netlist based on predefined digital library cells, incorporating a write port that clock-gates registers and multiplexes data using a selected word line, and employing tightly placed column decoding for read ports, along with controlled placement and optional features like scan testing and reset functionality, to optimize the storage array implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If standard SRAMs or vendor-provided SRAM compilers are used for multi-ported storage arrays, then design simplicity is maintained, but performance is poor and device complexity increases
Solution Approach 1:
The patent changes the fundamental parameter of how storage arrays are generated - transitioning from behavioral RTL descriptions to physically-driven netlist generation. This involves changing the abstraction level from behavioral to structural, and the generation method from random logic synthesis to direct netlist construction based on predefined digital library cells, thereby improving performance while maintaining design simplicity.
Solution Approach 2:
The patent substitutes the traditional mechanical/digital flow approach (RTL description → synthesis → placement and routing) with a direct physically-driven netlist generation approach. This replacement eliminates the intermediate synthesis step that cannot exploit array structure, directly generating optimized netlists from library cells that inherently support multi-ported operations.
2Adaptability or versatility
If behavioral RTL description and random logic synthesis are used, then design flexibility is maintained, but device complexity increases and performance deteriorates
Solution Approach 1:
The patent changes the generation parameter from behavioral description to physical netlist construction, using predefined digital library cells that encode optimized structures for multi-ported operations. This transformation maintains design flexibility through configurable parameters while producing circuits with reduced complexity by leveraging pre-optimized cell designs rather than synthesizing from scratch.
Solution Approach 2:
The patent applies preliminary action by pre-defining digital library cells with optimized structures for multi-ported storage arrays. These pre-characterized cells incorporate optimal logic structures, timing optimizations, and resource allocations, which are then directly instantiated in the netlist generation process, eliminating the need for complex synthesis operations.
3Adaptability or versatility
If high-degree multiplexing is implemented in RTL, then multi-ported operation is achieved, but routing complexity increases and productivity decreases
Solution Approach 1:
The patent substitutes the RTL-based multiplexing approach with a physically-driven netlist generation approach that directly instantiates pre-optimized digital library cells. This replacement eliminates the need for complex multiplexing logic and routing operations, as the library cells are pre-configured to support multiple ports with optimized interconnections, dramatically reducing tool run times.
Solution Approach 2:
The patent uses copying by instantiating multiple instances of pre-defined digital library cells that represent optimized storage array structures. Instead of generating complex multiplexing logic from scratch, the system copies and configures proven cell designs that inherently support multi-ported operations, reducing both routing complexity and tool run times.
4Extent of automation
If standard digital flow is used for SCM generation, then design automation is maintained, but area efficiency is poor and power consumption is high
Solution Approach 1:
The patent changes the generation parameter from automated RTL synthesis to physically-driven netlist generation using predefined digital library cells. This transformation maintains automation through programmatic netlist generation while achieving area efficiency by instantiating pre-optimized cell structures that are specifically designed for compact multi-ported storage array implementations.
Solution Approach 2:
The patent substitutes the standard digital flow (RTL → synthesis → placement and routing) with a direct physically-driven netlist generation approach. This replacement eliminates the synthesis step that produces suboptimal area utilization, directly generating netlists from library cells that are pre-optimized for area efficiency in multi-ported storage array configurations.
5Extent of automation
If standard digital flow is used for SCM generation, then design automation is maintained, but power efficiency is poor
Solution Approach 1:
The patent changes the generation parameter from automated RTL synthesis to physically-driven netlist generation using predefined digital library cells. This transformation maintains automation while improving power efficiency by instantiating cell structures that are pre-optimized for low-power operation, including optimized clock gating, enable logic, and data path configurations specific to multi-ported storage arrays.
Solution Approach 2:
The patent substitutes the standard digital flow with a physically-driven approach that directly generates netlists from power-optimized library cells. This replacement eliminates the synthesis step that produces circuits with poor power characteristics, directly instantiating cells with optimized power management features such as clock gating, word line decoding, and enable logic that are specifically tuned for low-power multi-ported operation.
Data Source
AI summary
A method for using a storage array of a circuit includes generating a netlist of components and connections of circuitry of a storage array using behavioral description and random logic synthesis, using a write port to clock-gate each register of the storage array, and multiplexing data based on a selected word line of the storage array.