Multi-Precision Convolution Circuit Using Shifted Product-Sum Accumulation
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Solution Overview
Problem
Existing convolution operation methods require separate hardware circuits for different accuracy modes, leading to inefficient use of resources and increased circuit size when switching between modes, particularly in AI inference processing.
Innovation Solution
A data processing equipment and method that performs convolution operations using a product-sum operation unit, shifter, sign operation unit, sign holding unit, and cumulative addition unit to efficiently handle multiple accuracy modes with minimal hardware by time-dividing input data into upper and lower bits and reflecting signs in output results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate hardware circuits are prepared for each convolution operation accuracy mode, then each mode can be processed with dedicated optimization, but the circuit area and hardware resources increase significantly
Solution Approach 1:
The patent implements a universal product-sum operation circuit that can perform convolution operations at multiple accuracy modes (4-bit, 8-bit, 16-bit) using the same hardware circuit. The circuit uses configurable data width settings and bit shifting mechanisms to adapt to different precision requirements, eliminating the need for separate dedicated circuits for each accuracy mode while maintaining optimized performance for each.
Solution Approach 2:
The patent changes operational parameters such as data width, shift amounts, and accumulation settings to enable the same circuit to operate at different accuracy modes. By dynamically adjusting these parameters rather than redesigning the circuit for each mode, the system achieves multi-precision capability with a single hardware design, significantly reducing circuit area.
2Device complexity
If the maximum value of iFmap is divided into several blocks for processing, then the circuit scale is reduced, but the processing time and complexity increase
Solution Approach 1:
The patent segments the convolution operation into manageable blocks of input feature map data, processing each block through the product-sum operation circuit. This segmentation allows the circuit to handle large iFmaps without requiring proportional increases in circuit scale, as each block is processed independently through the same configurable circuit architecture.
Solution Approach 2:
The patent implements dynamic processing where the circuit can adaptively adjust its operation based on the input data characteristics and required accuracy mode. The system dynamically configures data width, shift operations, and accumulation parameters to optimize processing efficiency for each specific block and mode combination, reducing overall processing time compared to static block processing approaches.
3Measurement precision
If a product-sum operation circuit supporting maximum accuracy mode is prepared, then high precision convolution operations can be performed, but the use efficiency of logic and memory deteriorates in lower accuracy modes
Solution Approach 1:
The patent employs parameter change mechanisms where the same product-sum operation circuit dynamically adjusts its operational parameters (data width, shift amounts, accumulation settings) to match the required accuracy mode. This allows the circuit to maintain high efficiency across all modes by configuring itself appropriately rather than being optimized for a single maximum accuracy mode, thereby improving overall productivity.
Solution Approach 2:
The patent designs a universal product-sum operation circuit that efficiently handles multiple accuracy modes (4-bit, 8-bit, 16-bit) with a single hardware implementation. The circuit uses configurable data path widths and shift operations to adapt to different precision requirements, ensuring that logic and memory resources are utilized efficiently across all modes rather than being over-designed for maximum accuracy only.
Data Source
AI summary
A data processing equipment 1 performs a convolution operation on two items of input data having a width of 2M* N-bit, where N is a positive integer and M is an integer of 0 or more, with a minimum accuracy of a convolution operation being N bits, in a case of performing processing corresponding to a plurality of the Ms that are consecutive, performs a product-sum operation of the minimum accuracy, in a case in which a value of the M is not 0, performs shift processing on an operation result of a product-sum operation of the minimum accuracy and performs an operation of a sign in a convolution operation of the input data, reflects a sign held until a reset signal is received in an output of the shift processing according to a value of the M, and cumulatively adds an output of the shift processing in which a sign is reflecte.