Multi-Precision Dot-Product Accelerator With Centralized Reconfiguration
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Solution Overview
Problem
Conventional multi-precision dot-product circuits face inefficiencies due to precision-dependent multiplexers and reconfiguration logic replication across all multipliers, leading to significant area and energy overhead, as they compute individual precision-dependent multiplier products and sum them using an adder tree sized for the largest bit-width.
Innovation Solution
The solution involves removing precision-dependent multiplexers and reconfiguration logic from the multipliers and placing them after the adder tree, focusing on reaching the final dot product without explicitly completing intermediate calculations, which reduces the number of overall multiplexers and narrows the adder tree width, thereby lowering area and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If precision-dependent multiplexers and reconfiguration logic are replicated across all multipliers to support multiple precision modes, then adaptability is improved, but device complexity and area increase
Solution Approach 1:
The patent extracts the precision-dependent multiplexers and reconfiguration logic from individual multiplier units and relocates them to a centralized position after the adder tree. This extraction eliminates the need for replication across all multipliers, reducing device complexity while preserving multi-precision adaptability through centralized control.
Solution Approach 2:
The patent implements a universal multiplier design that can operate across multiple precision modes without requiring precision-specific configuration logic in each multiplier unit. The centralized multiplexer system provides universal control for selecting precision modes, allowing the same hardware to serve multiple functions across different precision requirements.
2Adaptability or versatility
If adder tree is sized for the largest bit-width to support all precision modes, then adaptability is improved, but area and energy consumption increase
Solution Approach 1:
The patent introduces dynamic sizing of the adder tree by placing multiplexers at the output of each multiplier to selectively route intermediate results. This allows the adder tree to dynamically adapt its effective width based on the selected precision mode, rather than being statically sized for the maximum bit-width, thereby reducing area while maintaining adaptability.
Solution Approach 2:
The patent applies local quality by allowing different parts of the computation pipeline to operate at different precision levels simultaneously. The multiplexers enable selective routing of intermediate results at appropriate precision levels to the adder tree, so that only the necessary bit-width is processed at each stage, optimizing area usage while supporting all precision modes.
3Manufacturing precision
If intermediate precision-dependent products are explicitly computed and summed, then manufacturing precision is improved, but use of energy increases
Solution Approach 1:
The patent applies skipping by allowing intermediate precision-dependent products to be implicitly computed through the adder tree without explicit multiplication and summation steps for each precision mode. The multiplexers enable the circuit to rush through the computation by directly routing pre-computed intermediate results to the appropriate adder tree inputs, maintaining accuracy while reducing energy consumption by avoiding redundant computation steps.
Data Source
AI summary
A configurable integrated circuit to compute vector dot products between a first N-bit vector and a second N-bit vector in a plurality of precision modes. An embodiment includes M slices, each of which calculates the vector dot products between a corresponding segment of the first and the second N-bit vectors. Each of the slices outputs intermediary multiplier results for the lower precision modes, but not for highest precision mode. A plurality of adder trees to sum up the plurality of intermediate multiplier results, with each adder tree producing a respective adder out result. An accumulator to merge the adder out result from a first adder tree with the adder out result from a second adder tree to produce the vector dot product of the first and the second N-bit vector in the highest precision mode.